filter.vhd

MATLAB辅助设计数字滤波器源代码

-- -------------------------------------------------------------
--
-- Module: filter
--
-- Generated by MATLAB(R) 7.6 and the Filter Design HDL Coder 2.2.
--
-- Generated on: 2009-03-17 11:58:46
--
-- -------------------------------------------------------------

-- -------------------------------------------------------------
-- HDL Code Generation Options:
--
-- TargetLanguage: VHDL
-- FIRAdderStyle: tree
-- TargetDirectory: F:\MATLAB\Filter
-- CoefficientSource: ProcessorInterface
-- TestBenchStimulus: chirp impulse noise ramp step 
--
-- Filter Settings:
--
-- Discrete-Time FIR Filter (real)
-- -------------------------------
-- Filter Structure  : Direct-Form FIR
-- Filter Length     : 31
-- Stable            : Yes
-- Linear Phase      : Yes (Type 1)
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
ENTITY filter IS
   PORT( clk                             :   IN    std_logic; 
         clk_enable                      :   IN    std_logic; 
         reset                           :   IN    std_logic; 
         filter_in                       :   IN    real; -- double
         write_enable                    :   IN    std_logic; 
         write_done                      :   IN    std_logic; 
         write_address                   :   IN    real; -- double
         coeffs_in                       :   IN    real; -- double
         filter_out                      :   OUT   real  -- double
         );

END filter;


----------------------------------------------------------------
--Module Architecture: filter
----------------------------------------------------------------
ARCHITECTURE rtl OF filter IS
  -- Local Functions
  -- Type Definitions
  TYPE delay_pipeline_type IS ARRAY (NATURAL range <>) OF real; -- double
  TYPE register_file_type IS ARRAY (NATURAL range <>) OF real; -- double
  -- Constants
  -- Signals
  SIGNAL delay_pipeline                   : delay_pipeline_type(0 TO 30) := (0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0); -- double
  SIGNAL write_address_reg                : real := 0.0; -- double
  SIGNAL coeffs_in_reg                    : real := 0.0; -- double
  SIGNAL write_enable_reg                 : std_logic; -- boolean
  SIGNAL write_done_reg                   : std_logic; -- boolean
  SIGNAL coeffs_assigned                  : register_file_type(0 TO 30) := (0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0); -- double
  SIGNAL coeffs_temp                      : register_file_type(0 TO 30) := (0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0); -- double
  SIGNAL coeffs_regs                      : register_file_type(0 TO 30) := (0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0); -- double
  SIGNAL coeffs_shadow                    : register_file_type(0 TO 30) := (0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0); -- double
  SIGNAL product31                        : real := 0.0; -- double
  SIGNAL product30                        : real := 0.0; -- double
  SIGNAL product29                        : real := 0.0; -- double
  SIGNAL product28                        : real := 0.0; -- double
  SIGNAL product27                        : real := 0.0; -- double
  SIGNAL product26                        : real := 0.0; -- double
  SIGNAL product25                        : real := 0.0; -- double
  SIGNAL product24                        : real := 0.0; -- double
  SIGNAL product23                        : real := 0.0; -- double
  SIGNAL product22                        : real := 0.0; -- double
  SIGNAL product21                        : real := 0.0; -- double
  SIGNAL product20                        : real := 0.0; -- double
  SIGNAL product19                        : real := 0.0; -- double
  SIGNAL product18                        : real := 0.0; -- double
  SIGNAL product17                        : real := 0.0; -- double
  SIGNAL product16                        : real := 0.0; -- double
  SIGNAL product15                        : real := 0.0; -- double
  SIGNAL product14                        : real := 0.0; -- double
  SIGNAL product13                        : real := 0.0; -- double
  SIGNAL product12                        : real := 0.0; -- double
  SIGNAL product11                        : real := 0.0; -- double
  SIGNAL product10                        : real := 0.0; -- double
  SIGNAL product9                         : real := 0.0; -- double
  SIGNAL product8                         : real := 0.0; -- double
  SIGNAL product7                         : real := 0.0; -- double
  SIGNAL product6                         : real := 0.0; -- double
  SIGNAL product5                         : real := 0.0; -- double
  SIGNAL product4                         : real := 0.0; -- double
  SIGNAL product3                         : real := 0.0; -- double
  SIGNAL product2                         : real := 0.0; -- double
  SIGNAL product1                         : real := 0.0; -- double
  SIGNAL sum1_1                           : real := 0.0; -- double
  SIGNAL sum1_2                           : real := 0.0; -- double
  SIGNAL sum1_3                           : real := 0.0; -- double
  SIGNAL sum1_4                           : real := 0.0; -- double
  SIGNAL sum1_5                           : real := 0.0; -- double
  SIGNAL sum1_6                           : real := 0.0; -- double
  SIGNAL sum1_7                           : real := 0.0; -- double
  SIGNAL sum1_8                           : real := 0.0; -- double
  SIGNAL sum1_9                           : real := 0.0; -- double
  SIGNAL sum1_10                          : real := 0.0; -- double
  SIGNAL sum1_11                          : real := 0.0; -- double
  SIGNAL sum1_12                          : real := 0.0; -- double
  SIGNAL sum1_13                          : real := 0.0; -- double
  SIGNAL sum1_14                          : real := 0.0; -- double
  SIGNAL sum1_15                          : real := 0.0; -- double
  SIGNAL sum2_1                           : real := 0.0; -- double
  SIGNAL sum2_2                           : real := 0.0; -- double
  SIGNAL sum2_3                           : real := 0.0; -- double
  SIGNAL sum2_4                           : real := 0.0; -- double
  SIGNAL sum2_5                           : real := 0.0; -- double
  SIGNAL sum2_6                           : real := 0.0; -- double
  SIGNAL sum2_7                           : real := 0.0; -- double
  SIGNAL sum2_8                           : real := 0.0; -- double
  SIGNAL sum3_1                           : real := 0.0; -- double
  SIGNAL sum3_2                           : real := 0.0; -- double
  SIGNAL sum3_3                           : real := 0.0; -- double
  SIGNAL sum3_4                           : real := 0.0; -- double
  SIGNAL sum4_1                           : real := 0.0; -- double
  SIGNAL sum4_2                           : real := 0.0; -- double
  SIGNAL sum5_1                           : real := 0.0; -- double
  SIGNAL output_register                  : real := 0.0; -- double


BEGIN

  -- Block Statements
  Delay_Pipeline_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      delay_pipeline(0 TO 30) <= (OTHERS => 0.0000000000000000E+000);
    ELSIF clk'event AND clk = '1' THEN
      IF clk_enable = '1' THEN
        delay_pipeline(0) <= filter_in;
        delay_pipeline(1 TO 30) <= delay_pipeline(0 TO 29);
      END IF;
    END IF; 
  END PROCESS Delay_Pipeline_process;


  Input_Register_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      write_enable_reg <= '0';
      write_done_reg <= '0';
      write_address_reg <= 0.0000000000000000E+000;
      coeffs_in_reg <= 0.0000000000000000E+000;
    ELSIF clk'event AND clk = '1' THEN
      IF clk_enable = '1' THEN
        write_enable_reg <= write_enable;
        write_done_reg <= write_done;
        write_address_reg <= write_address;
        coeffs_in_reg <= coeffs_in;
      END IF;
    END IF; 
  END PROCESS Input_Register_process;

  coeffs_assigned(0) <= coeffs_in_reg WHEN ( write_address_reg = 0.0000000000000000E+000 ) ELSE
                        coeffs_regs(0);
  coeffs_assigned(1) <= coeffs_in_reg WHEN ( write_address_reg = 1.0000000000000000E+000 ) ELSE
                        coeffs_regs(1);
  coeffs_assigned(2) <= coeffs_in_reg WHEN ( write_address_reg = 2.0000000000000000E+000 ) ELSE
                        coeffs_regs(2);
  coeffs_assigned(3) <= coeffs_in_reg WHEN ( write_address_reg = 3.0000000000000000E+000 ) ELSE
                        coeffs_regs(3);
  coeffs_assigned(4) <= coeffs_in_reg WHEN ( write_address_reg = 4.0000000000000000E+000 ) ELSE
                        coeffs_regs(4);
  coeffs_assigned(5) <= coeffs_in_reg WHEN ( write_address_reg = 5.0000000000000000E+000 ) ELSE
                        coeffs_regs(5);
  coeffs_assigned(6) <= coeffs_in_reg WHEN ( write_address_reg = 6.0000000000000000E+000 ) ELSE
                        coeffs_regs(6);
  coeffs_assigned(7) <= coeffs_in_reg WHEN ( write_address_reg = 7.0000000000000000E+000 ) ELSE
                        coeffs_regs(7);
  coeffs_assigned(8) <= coeffs_in_reg WHEN ( write_address_reg = 8.0000000000000000E+000 ) ELSE
                        coeffs_regs(8);
  coeffs_assigned(9) <= coeffs_in_reg WHEN ( write_address_reg = 9.0000000000000000E+000 ) ELSE
                        coeffs_regs(9);
  coeffs_assigned(10) <= coeffs_in_reg WHEN ( write_address_reg = 1.0000000000000000E+001 ) ELSE
                         coeffs_regs(10);
  coeffs_assigned(11) <= coeffs_in_reg WHEN ( write_address_reg = 1.1000000000000000E+001 ) ELSE
                         coeffs_regs(11);
  coeffs_assigned(12) <= coeffs_in_reg WHEN ( write_address_reg = 1.2000000000000000E+001 ) ELSE
                         coeffs_regs(12);
  coeffs_assigned(13) <= coeffs_in_reg WHEN ( write_address_reg = 1.3000000000000000E+001 ) ELSE
                         coeffs_regs(13);
  coeffs_assigned(14) <= coeffs_in_reg WHEN ( write_address_reg = 1.4000000000000000E+001 ) ELSE
                         coeffs_regs(14);
  coeffs_assigned(15) <= coeffs_in_reg WHEN ( write_address_reg = 1.5000000000000000E+001 ) ELSE