📄 phy.c

📁 ZIGBEE 2006协议栈 BAT测试代码 RADIO PULSE MG2455
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	}
	
	xINTCON = 0xFA;			// 1111_1010. RxStart=0, Modem-On=0
	xTST2 = 0xFF;
	xTST13 = 0x00;
	xTST15 = 0x00;
	xCLKON1 = 0x7B;			// TSTCLK is OFF
}

void ZHAL_MODEM_INIT()
{
	if(xCHIPID == 0x91)
	{
		ZHAL_MODEM_INIT_CHIP91(Mode_19MHz);
	}
	else
	{
		ZHAL_MODEM_INIT_CHIP92(Mode_19MHz);
	}
}


//-- RETURN
//	255	: Max Energy (High)
//	0	: Min Energy (Low)
UINT8 ZHAL_ED_LEVEL_GET()
{
	INT8		dBm;
	UINT16	Tmp16;
	UINT8	Level;

	dBm = xAGCSTS2;

	// RSSI : LQI type, 0~255, 255=high power
	if(dBm > 0)
	{
		Level = 255;
	}
	else if(dBm > -100)
	{
		Tmp16 = 100 + dBm;
		Tmp16 *= 255;
		Tmp16 /= 100;
		Level = Tmp16;
	}
	else
	{
		Level = 0;
	}

	return	Level;

}

INT8 ZHAL_ED_dBm_GET()
{
	INT8		dBm;

	dBm = xAGCSTS2;
	return	dBm;
}

	extern	UINT8	FlagRxAck;
	extern	UINT8	FlagTxDone;

//-	RETURN
//	0xE1	: Channel Access Failure
//	0xE9	: No Ack
//	0x00	: SUCCESS
UINT8 ZHAL_SEND_TXFIFO()

{
	UINT16	iw;
	UINT8	STA;

	xMTFCRP = 0;
	xMACDSN = xMTxFIFO(0+3);
	FlagTxDone = 0;
	FlagRxAck = 0;

	xPCMD0 &= 0xFB;
	for(iw=0 ; iw<5000 ; iw++)		// MAX 4.84 ms
	{
		if(FlagTxDone)
		{
			break;
		}

		if(iw == 4999)
		{		
			xPCMD0 |= 0x04;
			xSWRST &= 0xFE;
			xSWRST |= 0x01;
			xSWRST &= 0xFD;
			xSWRST |= 0x02;		
			STA = 0xE1;
			return	STA;
		}
	}

	STA = 0;
	if(xMTxFIFO(0+1) & 0x20)
	{		
		STA = 0xE9;
		for(iw=0 ; iw<1000 ; iw++)
		{
			if(FlagRxAck)
			{
				STA = 0;
				break;
			}
		}			
	}

	xMTFCRP = 0;
	
	return	STA;
}

	UINT8	X_BUFF[4];	
void ZHAL_SEND_ACK(UINT8 FP, UINT8 DSN)
{
	UINT8	INT_STA;
	UINT8	INT_IDX;
	UINT16	iw;
	UINT8	_MTFCRP;

	_MTFCRP = xMTFCRP;
	memcpy(X_BUFF, &xMTxFIFO(0), 4);

	xMTxFIFO(0) = 0x05;
	xMTxFIFO(1) = 0x02;
	if(FP)	xMTxFIFO(1) |= 0x10;
	xMTxFIFO(2) = 0x00;
	xMTxFIFO(3) = DSN;

	xMTFCRP = 0;
	xPCMD0 &= 0xFB;
	for(iw=0 ; iw<1000 ; iw++)
	{		
		INT_STA = xINTSTS & 0x0F;
		if(INT_STA)
		{
			INT_IDX = xINTIDX;
			EXIF &= 0xEF;
			if(INT_STA == 0x0D)	break;			
		}

		if(iw == 999)
		{		
			xPCMD0 |= 0x04;
			xSWRST &= 0xFE;
			xSWRST |= 0x01;
			xSWRST &= 0xFD;
			xSWRST |= 0x02;
		}
	}	
	memcpy(&xMTxFIFO(0), X_BUFF, 4);
	xMTFCRP = _MTFCRP;
	
}


//-	Enable : Test Mode Enable
// 0	: Normal Operation Mode
// 1	: Continuous RF Signal Generation Mode
//-	ModuleationEn : Modulated Signal Generation Enable
// 0	: Carrier Signal Generation
// 1	: Modulated Signal Generation with IFS(Inter-Frame-Space)
// 2	: Modulated Signal Generation without IFS(Inter-Frame-Space)
void ZHAL_TEST_TXOUT(UINT8 Ena, UINT8 ModulationEn)
{
	if(Ena)
	{
		//
		// Common Paramaters
		//	
		xPLLPD  = 0xFF;
		xPLLPU  = 0x00;
		xPCMD0	= 0x7F;		// 0111_1111
		xPCMD0	= 0xFE;		// 1111_1110
		xPCMD1	= 0xC4;		// 1100_0100
		xTXRFPD = 0xFF;
		xTXRFPU = 0x00;

		xRXRFPD = 0x00;
		xCLKON1 = 0x47;		// 0100_0111		

		if(ModulationEn == 1)
		{
			xTST0	= 0xFF;
			xTST2  	= 0x7F;
			xTST13 	= 0x7F;
			xTST0  	= 0xFF;
			xTST0  	= 0x7f;
			xTST15 	= 0x00;
			xTST0	= 0x7F;
		}
		else if(ModulationEn == 2)
		{
			xTST2	= 0x00;
			xTST13 	= 0x7F;
			xTST0  	= 0xFF;
			xTST0  	= 0x22;
		}
		else
		{
			xTST14	= 0x00;	// 0x5A = 700K, 0x40 = 500K
			xTST0 	= 0x20;
		}
	}
	else
	{
		xCLKON1 = 0x7B;
	
		// Watchdog Reset
		WDT |= 0x10;
		WDT |= 0x08;
		EA = 0;
	}	
}


// Rate = 0	:	250 Kbps
// Rate = 1	:	500 Kbps
// Rate = 2	:	1 Mbps
// Other		:	250 Kbps
void ZHAL_DATARATE_SET(UINT8 Rate)
{	
	xRXFRM1 &= 0x0F;	
	
	if(Rate == 1)			xRXFRM1 |= 0x50;	// bit[4]=1, bit[6]=1
	else if(Rate == 2)	xRXFRM1 |= 0xA0;	// bit[5]=1, bit[7]=1
}


//-----------------------------
// MAC_CTRL
//-----------------------------
// bit[7:5] : rsv				:: default=0
// bit[4] : prevent_ack_packet	:: default=0
// bit[3] : pan_coordinator		:: default=0
// bit[2] ; addr_decode			:: default=1
// bit[1] : auto_crc				:: default=1
// bit[0] : auto_ack			:: default=0
void ZHAL_MAC_CTRL_SET(UINT8 MacCtrl)
{
	xMACCTRL = MacCtrl;
}

void ZHAL_AUTO_CRC_SET(UINT8 Ena)
{
	if(Ena)	xMACCTRL |= 0x02;		// bit[1]=1
	else		xMACCTRL &= ~0x02;		// bit[1]=0
}

void ZHAL_ADDR_DECODE_SET(UINT8 Ena)
{
	if(Ena)	xMACCTRL |= 0x04;		// bit[2]=1
	else		xMACCTRL &= ~0x04;		// bit[2]=0
}

void ZHAL_COORDINATOR_SET(UINT8 Ena)
{
	if(Ena)	xMACCTRL |= 0x08;
	else		xMACCTRL &= ~0x08;
}


void ZHAL_PAN_ID_SET(UINT16 ID) {
	xPANID(0) = (UINT8) (ID) ;
	xPANID(1) = (UINT8) (ID >> 8) ;
}

void ZHAL_SHORT_ADDR_SET(UINT16 Addr) {
	xSHORTADDR(0) = (UINT8) (Addr) ;
	xSHORTADDR(1) = (UINT8) (Addr >> 8) ;
}

void ZHAL_IEEE_ADDR_SET(UINT8 *pAddr) {
	memcpy( &xEXTADDR(0), pAddr, 8);
}

void ZHAL_MAC_INIT()
{
	xMACCTRL = 0x16;
	xMRFCRP = 0;
	xMRFCWP = 0;
	xMTFCRP = 0;
	xMTFCWP = 0;
}



//-----------------------------------
//--	PowerLevel
//-----------------------------------
//	0 	: 10		dBm
//	1	: 9		dBm
//	2	: 8		dBm
//	3	: 7		dBm
//	4	: 6		dBm
//	5	: 5		dBm
//	6	: 4		dBm
//	7	: 3		dBm
//	8	: 2		dBm
//	9	: 1		dBm
//	10	: 0		dBm
//	11	: -5		dBm
//	12	: -7		dBm
//	13	: -10	dBm
//	14	: -15	dBm
//	15	: -20	dBm
//	16	: -30 	dBm
//	17	: -40	dBm
//	18	: -50	dBm
//-----------------------------------
void ZHAL_TXPOWER_SET_CHIP91(UINT8 PowerLevel) 
{

	switch(PowerLevel)
	{
		case 0	: xTXPA=0x9F; xTXDA=0xFF; xTXMIX=0x6F;	break;
		case 1	: xTXPA=0x96; xTXDA=0xF8; xTXMIX=0x6F;	break;
		case 2	: xTXPA=0x92; xTXDA=0xF8; xTXMIX=0x6F;	break;
		case 3	: xTXPA=0x90; xTXDA=0xF0; xTXMIX=0x6F;	break;
		case 4	: xTXPA=0x1C; xTXDA=0xF9; xTXMIX=0x6F;	break;
		case 5	: xTXPA=0x1A; xTXDA=0xFF; xTXMIX=0x6F;	break;
		case 6	: xTXPA=0x1B; xTXDA=0xE6; xTXMIX=0x6F;	break;
		case 7	: xTXPA=0x18; xTXDA=0xEE; xTXMIX=0x6F;	break;
		case 8	: xTXPA=0x18; xTXDA=0xE7; xTXMIX=0x6F;	break;
		case 9	: xTXPA=0x17; xTXDA=0xE5; xTXMIX=0x6F;	break;
		case 10	: xTXPA=0x16; xTXDA=0xE5; xTXMIX=0x6F;	break;
		case 11	: xTXPA=0x13; xTXDA=0xE4; xTXMIX=0x6F;	break;
		case 12	: xTXPA=0x12; xTXDA=0xE7; xTXMIX=0x6F;	break;
		case 13	: xTXPA=0x12; xTXDA=0xE1; xTXMIX=0x6F;	break;
		case 14	: xTXPA=0x11; xTXDA=0xE2; xTXMIX=0x6E;	break;
		case 15	: xTXPA=0x11; xTXDA=0xE1; xTXMIX=0x6D;	break;		
		case 16	: xTXPA=0x9F; xTXDA=0xFF; xTXMIX=0x1C;	break;
		case 17	: xTXPA=0x18; xTXDA=0xE7; xTXMIX=0x1C;	break;
		case 18	: xTXPA=0x13; xTXDA=0xE4; xTXMIX=0x18;	break;
		default	: xTXPA=0x9F; xTXDA=0xFF; xTXMIX=0x6F;	break;
	}

}



//-----------------------------------
//--	PowerLevel
//-----------------------------------
//	0 	: 8		dBm
//	1	: 8		dBm
//	2	: 8		dBm
//	3	: 7		dBm
//	4	: 6		dBm
//	5	: 5		dBm
//	6	: 4		dBm
//	7	: 3		dBm
//	8	: 2		dBm
//	9	: 1		dBm
//	10	: 0		dBm
//	11	: -5		dBm
//	12	: -7		dBm
//	13	: -10	dBm
//	14	: -15	dBm
//	15	: -20	dBm
//	16	: -30 	dBm
//	17	: -40	dBm
//	18	: -50	dBm
//-----------------------------------
void ZHAL_TXPOWER_SET_CHIP92(UINT8 PowerLevel) 
{
	switch(PowerLevel)
	{
		case 0	: xTXPA=0x9F; xTXDA=0xFF; xTXMIX=0x6F;	break;
		case 1	: xTXPA=0x9F; xTXDA=0xFF; xTXMIX=0x6F;	break;
		case 2	: xTXPA=0x9F; xTXDA=0xFF; xTXMIX=0x6F;	break;
		case 3	: xTXPA=0x9F; xTXDA=0xF5; xTXMIX=0x6F;	break;
		case 4	: xTXPA=0x9D; xTXDA=0xF0; xTXMIX=0x6F;	break;
		case 5	: xTXPA=0x9F; xTXDA=0xED; xTXMIX=0x6F;	break;
		case 6	: xTXPA=0x95; xTXDA=0xED; xTXMIX=0x6F;	break;
		case 7	: xTXPA=0x1F; xTXDA=0xF3; xTXMIX=0x6F;	break;
		case 8	: xTXPA=0x1F; xTXDA=0xEC; xTXMIX=0x6F;	break;
		case 9	: xTXPA=0x1E; xTXDA=0xEA; xTXMIX=0x6F;	break;
		case 10	: xTXPA=0x1C; xTXDA=0xE9; xTXMIX=0x6F;	break;
		case 11	: xTXPA=0x1E; xTXDA=0xE3; xTXMIX=0x6F;	break;
		case 12	: xTXPA=0x18; xTXDA=0xE3; xTXMIX=0x6F;	break;
		case 13	: xTXPA=0x18; xTXDA=0xE2; xTXMIX=0x6F;	break;		
		case 14	: xTXPA=0x13; xTXDA=0xE2; xTXMIX=0x6F;	break;		
		case 15	: xTXPA=0x12; xTXDA=0xE2; xTXMIX=0x6E;	break;
		case 16	: xTXPA=0x11; xTXDA=0xE2; xTXMIX=0x6D;	break;
		case 17	: xTXPA=0x9F; xTXDA=0xFF; xTXMIX=0x1C;	break;
		case 18	: xTXPA=0x18; xTXDA=0xE7; xTXMIX=0x1C;	break;
		default	: xTXPA=0x9F; xTXDA=0xFF; xTXMIX=0x6F;	break;
		
	}

}



void ZHAL_TXPOWER_SET(UINT8 PowerLevel)
{
	if(xCHIPID == 0x91)
	{
		ZHAL_TXPOWER_SET_CHIP91(PowerLevel);
	}
	else
	{
		ZHAL_TXPOWER_SET_CHIP92(PowerLevel);
	}
}






/////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////




void ZHAL_EXT0_INT_SET(UINT8 IntEna, UINT8 Priority, UINT8 TypeEdge) 
{
	UINT8	_EA;

	_EA = EA;
	EA = 0;	

	IT0 = TypeEdge;			// Edge=1, Level = 0
	PX0 = Priority;

	if(IntEna)	EX0 = 1;
	else 		EX0 = 0;

	EA = _EA;
}


void ZHAL_EXT1_INT_SET(UINT8 IntEna, UINT8 Priority, UINT8 TypeEdge) 
{
	UINT8	_EA;

	_EA = EA;
	EA = 0;	

	IT1 = TypeEdge;			// Edge=1, Level = 0
	PX1 = Priority;

	if(IntEna)	EX1 = 1;
	else 		EX1 = 0;

	EA = _EA;	
}

void ZHAL_RF_INT_SET(UINT8 IntEna, UINT8 Priority)
{
	UINT8	_EA;

	_EA = EA;
	EA = 0;

	RFIP = Priority;

	if(IntEna)	RFIE = 1;
	else			RFIE = 0;

	EA = _EA;
}


void ZHAL_RF_INT_CLEAR()
{
	UINT8	ReadReg;

	ReadReg = xINTSTS;	ReadReg = xINTIDX;	EXIF &= 0xEF;
	ReadReg = xINTSTS;	ReadReg = xINTIDX;	EXIF &= 0xEF;
	ReadReg = xINTSTS;	ReadReg = xINTIDX;	EXIF &= 0xEF;
	ReadReg = xINTSTS;	ReadReg = xINTIDX;	EXIF &= 0xEF;
}


void ZHAL_SYSTEM_INTERRUPT(UINT8 IntEna)
{
	EA = IntEna;
}


/////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////


//-------------------------------------------------------
// Ena
//-------------------------------------------------------
// bit[1] : 1=Enable TRSWB(P1.6).	TxState=0, RxState=1
// bit[0] : 1=Enable TRSW(P1.7).		TxState=1, RxState=0
//-------------------------------------------------------
void ZHAL_TRSW_SET(UINT8 Ena)
{
	// TRSW = P1.7
	// TRSWB = P1.6

	xGPCNF4 &= 0x3F;
	if(Ena & 0x01)
	{	
		xGPCNF4 |= 0x40;
		xMONCON0 &= 0x0F;
	}

	xGPCNF4 &= 0xCF;
	if(Ena & 0x02)
	{
		xGPCNF4 |= 0x10;
	}
	
}


void ZHAL_PORT0_INOUT_SET(UINT8 Port, UINT8 OutEnable)
{
	UINT8	MASK_OR;
	UINT8	MASK_AND;
	UINT8	MASK_ENA;

	MASK_ENA = 1;
	switch(Port)
	{
		case 0x0	: MASK_OR = 0x01;	MASK_AND = 0xFE;	break;
		case 0x1	: MASK_OR = 0x02;	MASK_AND = 0xFD;	break;
		case 0x2	: MASK_OR = 0x04;	MASK_AND = 0xFB;	break;
		case 0x3	: MASK_OR = 0x08;	MASK_AND = 0xF7;	break;
		case 0x4	: MASK_OR = 0x10;	MASK_AND = 0xEF;	break;
		case 0x5	: MASK_OR = 0x20;	MASK_AND = 0xDF;	break;
		case 0x6	: MASK_OR = 0x40;	MASK_AND = 0xBF;	break;
		case 0x7	: MASK_OR = 0x80;	MASK_AND = 0x7F;	break;
		case 0xA	: MASK_OR = 0xFF;	MASK_AND = 0x00;	break;
		default	: MASK_ENA = 0;							break;
	}

	if(MASK_ENA)
	{
		if(Port == 0x0A)	{	P0REN = 0;	P0OEN = 0;	}		// MG2450ES
	
		if(OutEnable)	{	P0REN |= MASK_OR;	P0OEN &= MASK_AND;	}
		else				{	P0REN &= MASK_AND;	P0OEN |= MASK_OR;	}
	}
}


void ZHAL_PORT1_INOUT_SET(UINT8 Port, UINT8 OutEnable)
{
	UINT8	MASK_OR;
	UINT8	MASK_AND;
	UINT8	MASK_ENA;

	MASK_ENA = 1;
	switch(Port)
	{
		case 0x0	: MASK_OR = 0x01;	MASK_AND = 0xFE;	break;
		case 0x1	: MASK_OR = 0x02;	MASK_AND = 0xFD;	break;
		case 0x2	: MASK_OR = 0x04;	MASK_AND = 0xFB;	break;
		case 0x3	: MASK_OR = 0x08;	MASK_AND = 0xF7;	break;
		case 0x4	: MASK_OR = 0x10;	MASK_AND = 0xEF;	break;	// MG2450ES
		case 0x5	: MASK_OR = 0x20;	MASK_AND = 0xDF;	break;	// MG2450ES
		case 0x6	: MASK_OR = 0x40;	MASK_AND = 0xBF;	break;	// MG2450ES
		case 0x7	: MASK_OR = 0x80;	MASK_AND = 0x7F;	break;	// MG2450ES
		case 0xA	: MASK_OR = 0xFF;	MASK_AND = 0x00;	break;
		default	: MASK_ENA = 0;							break;
	}

	if(MASK_ENA)
	{
		if(Port == 0x0A)	{	P1REN = 0;	P1OEN = 0;	}		// MG2450ES
		
		if(OutEnable)	{	P1REN |= MASK_OR;	P1OEN &= MASK_AND;	}
		else				{	P1REN &= MASK_AND;	P1OEN |= MASK_OR;	}
	}	

}

void ZHAL_PORT3_INOUT_SET(UINT8 Port, UINT8 OutEnable)
{
	UINT8	MASK_OR;
	UINT8	MASK_AND;
	UINT8	MASK_ENA;

	MASK_ENA = 1;
	switch(Port)
	{
		case 0x0	: MASK_OR = 0x01;	MASK_AND = 0xFE;	break;
		case 0x1	: MASK_OR = 0x02;	MASK_AND = 0xFD;	break;
		case 0x2	: MASK_OR = 0x04;	MASK_AND = 0xFB;	break;
		case 0x3	: MASK_OR = 0x08;	MASK_AND = 0xF7;	break;
		case 0x4	: MASK_OR = 0x10;	MASK_AND = 0xEF;	break;	// MG2450ES
		case 0x5	: MASK_OR = 0x20;	MASK_AND = 0xDF;	break;	// MG2450ES
		case 0x6	: MASK_OR = 0x40;	MASK_AND = 0xBF;	break;	// MG2450ES
		case 0x7	: MASK_OR = 0x80;	MASK_AND = 0x7F;	break;	// MG2450ES
		case 0xA	: MASK_OR = 0xFF;	MASK_AND = 0x00;	break;		
		default	: MASK_ENA = 0;							break;
	}

	if(MASK_ENA)
	{
		if(Port == 0x0A)	{	P3REN = 0;	P3OEN = 0;	}		// MG2450ES
	
		if(OutEnable)	{	P3REN |= MASK_OR;	P3OEN &= MASK_AND;	}
		else				{	P3REN &= MASK_AND;	P3OEN |= MASK_OR;	}
	}	
	
}


//-- VFifoSrc
//	0	: I2S
//	1	: SPI
//	2	: UART0
//	3	: UART1
void ZHAL_VFIFO_MUX_SET(UINT8 VFifoSrc)
{
	xSRCCTL &= 0x9F;	// bit[6:5]=0
	xSRCCTL |= (VFifoSrc & 0x03) << 5;

//	xVTF_CTL |= 0x01;
//	xVTF_CTL |= 0x02;
//	xVRF_CTL |= 0x01;
//	xVRF_CTL |= 0x02;
//	while(xVTF_STS);
}
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