phy.c

ZIGBEE 2006协议栈 BAT测试代码 RADIO PULSE MG2455

/*******************************************************************************
	- Chip		: MG24500/55
	- Author		: RadioPulse Inc, 2007.
	- Date		: 2007-07-02
	- Version		: VER 1.0	
*******************************************************************************/

#include "INCLUDE_TOP.h"


//
//	xPDM
//	bit[7]	: Analog Regulator. 1=Voltage is changed (1.5V <-> 1.8V)
//	bit[6]	: Digital Regulator. 1=Voltage is changed (1.5V <-> 1.8V)
//
//	When MSV pin of MG245X is HIGH(It means 1.8V input)
//	===> if bit[7]=1, Regulator Output Voltage is 1.5V.(1.5V is used in core block).
//	When MSV pin of MG245X is LOW(It means 1.5V input)
//	===> if bit[7]=1, Regulator Output Voltage is 1.8V.(1.8V is used in core block).
//
void ZHAL_REGULATOR_SET(UINT8 ChangeAnalog, UINT8 ChangeDigital)
{
	if(ChangeAnalog)	xPDM |= 0x80;		// bit[7]=1
	else					xPDM &= ~0x80;		// bit[7]=0

	if(ChangeDigital)		xPDM |= 0x40;		// bit[6]=1
	else					xPDM &= ~0x40;		// bit[6]=0
}




void ZHAL_CLOCK_BLOCK_SET(UINT8 EnaCodec, UINT8 EnaAES)
{
	//--------------------------------------------------------------------
	//	BIT[7]	BIT[6]	BIT[5]	BIT[4]	BIT[3]	BIT[2]	BIT[1]	BIT[0]
	//--------------------------------------------------------------------
	//	xCLKON0 ( 0xff)
	//	CCLK	CCCLK	CPCLK	AESCLK	MTCLK	MRCLK	REGCLK	ECHOCLK
	//					(PERI)									(CODEC)
	//--------------------------------------------------------------------
	
	if(EnaCodec)
			xCLKON0 |=  (1<<0);
  	else		xCLKON0 &= ~(1<<0);
	
	if(EnaAES)
			xCLKON0 |= (1<<4);
   	else		xCLKON0 &= ~(1<<4);
}


//-- EnaCLKPLL
//	1 	: Enable CLKPLL to use 19.2MHz XTAL CLOCK.
//	0	: Disable CLKPLL to use default XTAL CLOCK.
void ZHAL_CLOCK_PLL_SET(UINT8 EnaCLKPLL)
{
	//-------------------------------------------------------------------------------------
	//	xCKPLL
	//-------------------------------------------------------------------------------------
	//	BIT[7]	BIT[6]		BIT[5]		BIT[4]		BIT[3]		BIT[2:1]			BIT[0]
	//	Rsvd	CKPLL_CH	CKPLL_OK	CKPLLEN	CKPLLRSTB		XTALSEL[1:0]		RCOSCDIV2
	//-------------------------------------------------------------------------------------
	
	UINT8	_CKPLL;

	_CKPLL = xCKPLL;
	
	if(EnaCLKPLL)
	{
		_CKPLL |= ( 1 << 4); 	// CKPLLEN ON
		_CKPLL |= ( 1 << 3);	// Release RESET# 

		xCKPLL = _CKPLL;

		while(1)	// 
		{
			if(xCKPLL & 0x20) break;	// PLL OK CONFIRM
		}

		xCKPLL |= (1<<2);			// CLOCK SWITCHING TO PLLOUT
	}
	else
	{
		_CKPLL &= ~(1 <<2);	// CLK = XTAL	
		_CKPLL &= ~(1 <<4); 	// CKPLLEN OFF
		_CKPLL &= ~(1 <<3);	// Initialte RESET#
		
		xCKPLL = _CKPLL;		// CLOCK SWITCHING TO 16MHZ
	}
}


//-- Ena16MHz
//	1 	: System Clock 16MHz
//	0	: System Clock 8MHz
void ZHAL_CLOCK_16MHz_SET(UINT8 Ena16MHz)
{
	if(Ena16MHz)	xCLKDIV0 = 0x00;
	else				xCLKDIV0 = 0xFF;
}



	UINT8	Mode_19MHz;			// 19.2MHz CLK PLL


void ZHAL_HW_INIT(UINT8 Ena19MHz, UINT8 VoltChange)
{	
	Mode_19MHz = 0;	
	if(Ena19MHz)
	{	
		ZHAL_CLOCK_PLL_SET(1);
		Mode_19MHz = 1;
	}

	if(VoltChange)
	{
		ZHAL_REGULATOR_SET(1, 1);
	}
}

void SetDelay(UINT16 delay1, UINT16 delay2) 
{
	UINT16 	cnt1;
	UINT16	cnt2;
	
	cnt1 = delay1;	
	cnt2 = delay2;	
	
	while (cnt1) 
	{
		while (cnt2) 
		{
			cnt2	= cnt2-1;		
		}		
		cnt1 	= cnt1-1;		
		cnt2 	= delay2;	
	}
}


void ZHAL_CHANNEL_SET_CHIP91_XTAL19(UINT8 CH)
{
	UINT16		Counter;
	UINT8		STA;
	UINT16		i;	
	UINT8		AD;		// PLLADIV
	UINT8		F3;		// PLLFRAC3
	UINT8		F4;		// PLLFRAC4

	switch(CH)
	{
		case 0x0B : AD = 0x01; F3 = 0x05; F4 = 0x30;	xPLLCP = 0x22;break;
		case 0x0C : AD = 0x01; F3 = 0x0A; F4 = 0x70;	xPLLCP = 0x22;break;
		case 0x0D : AD = 0x01; F3 = 0x0F; F4 = 0xA0;	xPLLCP = 0x22;break;
		case 0x0E : AD = 0x01; F3 = 0x14; F4 = 0xD0;	xPLLCP = 0x22;break;
		case 0x0F : AD = 0x02; F3 = 0xB6; F4 = 0x10;	xPLLCP = 0x22;break;
		case 0x10 : AD = 0x02; F3 = 0xBB; F4 = 0x40;	xPLLCP = 0x22;break;
		case 0x11 : AD = 0x02; F3 = 0xC0; F4 = 0x70;	xPLLCP = 0x22;break;
		case 0x12 : AD = 0x01; F3 = 0x29; F4 = 0xB0;	xPLLCP = 0x22;break;
		case 0x13 : AD = 0x01; F3 = 0x2E; F4 = 0xE0;	xPLLCP = 0x22;break;
		case 0x14 : AD = 0x01; F3 = 0x34; F4 = 0x10;	xPLLCP = 0x22;break;
		case 0x15 : AD = 0x01; F3 = 0x39; F4 = 0x50;	xPLLCP = 0x22;break;
		case 0x16 : AD = 0x01; F3 = 0x3E; F4 = 0x80;	xPLLCP = 0x22;break;
		case 0x17 : AD = 0x02; F3 = 0xDF; F4 = 0xB0;	xPLLCP = 0x22;break;
		case 0x18 : AD = 0x02; F3 = 0xE4; F4 = 0xF0;	xPLLCP = 0x22;break;
		case 0x19 : AD = 0x02; F3 = 0xEA; F4 = 0x20;	xPLLCP = 0x22;break;
		case 0x1A : AD = 0x01; F3 = 0x53; F4 = 0x50;	xPLLCP = 0x22;break;
		default	  : AD = 0x01; F3 = 0x2E; F4 = 0xE0;	xPLLCP = 0x22;break;
	}
	
	xPLLADIV = AD;
	xPLLBDIV = 0x06;			// 19.2MHz specific
	xPLLFRAC3 = F3;
	xPLLFRAC4 = F4;

	Counter = 0;
	while(1)
	{	
		Counter += 100;
		xPLLADFC	= 0xEC;
		for(i=0 ; i<Counter ; i++);
		xPLLADFC	= 0xEC;

		STA = 0;
		for(i=0 ; i<0x1000 ; i++)
		{
			if(xPLLLD & 0x40)
			{
				STA = 1;
				break;
			}
		}

		if(STA)	break;
	}	

}




void ZHAL_CHANNEL_SET_CHIP91_XTAL16(UINT8 CH)
{
	UINT16		Counter;
	UINT8		STA;
	UINT16		i;	
	UINT8		AD;		// PLLADIV
	UINT8		F3;		// PLLFRAC3
	UINT8		F4;		// PLLFRAC4

	switch(CH)
	{
		case 0x0B : AD = 0x02; F3 = 0x06; F4 = 0x40;	xPLLCP = 0x22;break;
		case 0x0C : AD = 0x02; F3 = 0x0C; F4 = 0x80;	xPLLCP = 0x22;break;
		case 0x0D : AD = 0x02; F3 = 0x12; F4 = 0xC0;	xPLLCP = 0x22;break;
		case 0x0E : AD = 0x02; F3 = 0x19; F4 = 0x00;	xPLLCP = 0x22;break;
		case 0x0F : AD = 0x03; F3 = 0xBB; F4 = 0x40;	xPLLCP = 0x22;break;
		case 0x10 : AD = 0x03; F3 = 0xC1; F4 = 0x80;	xPLLCP = 0x22;break;
		case 0x11 : AD = 0x03; F3 = 0xC7; F4 = 0xC0;	xPLLCP = 0x22;break;
		case 0x12 : AD = 0x02; F3 = 0x32; F4 = 0x00;	xPLLCP = 0x22;break;
		case 0x13 : AD = 0x02; F3 = 0x38; F4 = 0x40;	xPLLCP = 0x22;break;
		case 0x14 : AD = 0x02; F3 = 0x3E; F4 = 0x80;	xPLLCP = 0x22;break;
		case 0x15 : AD = 0x02; F3 = 0x44; F4 = 0xC0;	xPLLCP = 0x22;break;
		case 0x16 : AD = 0x02; F3 = 0x4B; F4 = 0x00;	xPLLCP = 0x22;break;
		case 0x17 : AD = 0x03; F3 = 0xED; F4 = 0x40;	xPLLCP = 0x22;break;
		case 0x18 : AD = 0x03; F3 = 0xF3; F4 = 0x80;	xPLLCP = 0x22;break;
		case 0x19 : AD = 0x03; F3 = 0xF9; F4 = 0xC0;	xPLLCP = 0x22;break;
		case 0x1A : AD = 0x03; F3 = 0x00; F4 = 0x00;	xPLLCP = 0x2B;break;	
		default	  : AD = 0x02; F3 = 0x38; F4 = 0x40;	xPLLCP = 0x22;break;
	}

	xPLLADIV = AD;
	xPLLFRAC3 = F3;
	xPLLFRAC4 = F4;	

	Counter = 0;
	while(1)
	{	
		Counter += 100;
		xPLLADFC	= 0xEC;
		for(i=0 ; i<Counter ; i++);
		xPLLADFC	= 0xEC;

		STA = 0;
		for(i=0 ; i<0x1000 ; i++)
		{
			if(xPLLLD & 0x40)
			{
				STA = 1;
				break;
			}
		}

		if(STA)	break;
	}
}




void ZHAL_CHANNEL_SET_CHIP92_XTAL19(UINT8 CH)
{
	UINT16		Counter;
	UINT8		STA;
	UINT16		i;
	UINT8		F3, F4;

	xRXRFPD	= 0x00;
	xRXRFPU	= 0xFF;
	xTXRFPD	= 0x00;
	xTXRFPU	= 0xFF;

	switch(CH) 
	{
		case 11 	: F3 = 0x05; F4 = 0x30;	 xPLLADIV = (xPLLADIV & 0x30) | 0x01; break;
		case 12 	: F3 = 0x0A; F4 = 0x70;	 xPLLADIV = (xPLLADIV & 0x30) | 0x01; break;
		case 13 	: F3 = 0x0F; F4 = 0xA0;	 xPLLADIV = (xPLLADIV & 0x30) | 0x01; break;
		case 14 	: F3 = 0x14; F4 = 0xD0;	 xPLLADIV = (xPLLADIV & 0x30) | 0x01; break;
		case 15 	: F3 = 0xB6; F4 = 0x10;	 xPLLADIV = (xPLLADIV & 0x30) | 0x02; break;
		case 16 	: F3 = 0xBB; F4 = 0x40;	 xPLLADIV = (xPLLADIV & 0x30) | 0x02; break;
		case 17 	: F3 = 0xC0; F4 = 0x70;	 xPLLADIV = (xPLLADIV & 0x30) | 0x02; break;
		case 18 	: F3 = 0x29; F4 = 0xB0;	 xPLLADIV = (xPLLADIV & 0x30) | 0x01; break;
		case 19 	: F3 = 0x2E; F4 = 0xE0;	 xPLLADIV = (xPLLADIV & 0x30) | 0x01; break;
		case 20 	: F3 = 0x34; F4 = 0x10;	 xPLLADIV = (xPLLADIV & 0x30) | 0x01; break;
		case 21 	: F3 = 0x39; F4 = 0x50;	 xPLLADIV = (xPLLADIV & 0x30) | 0x01; break;
		case 22 	: F3 = 0x3E; F4 = 0x80;	 xPLLADIV = (xPLLADIV & 0x30) | 0x01; break;
		case 23 	: F3 = 0xDF; F4 = 0xB0;	 xPLLADIV = (xPLLADIV & 0x30) | 0x02; break;
		case 24 	: F3 = 0xE4; F4 = 0xF0;	 xPLLADIV = (xPLLADIV & 0x30) | 0x02; break;
		case 25 	: F3 = 0xEA; F4 = 0x20;	 xPLLADIV = (xPLLADIV & 0x30) | 0x02; break;
		case 26 	: F3 = 0x53; F4 = 0x50;	 xPLLADIV = (xPLLADIV & 0x30) | 0x01; break;
		default 	: F3 = 0x2E; F4 = 0xE0;	 xPLLADIV = (xPLLADIV & 0x30) | 0x01; break;
	}

	xPLLBDIV = 0x06;
	xPLLCP = 0x32;
	xPLLFRAC3	= F3;
	xPLLFRAC4	= F4;

	Counter = 0;
	while(1)
	{	
		Counter += 100;
		xPLLADFC	= 0xEF;
		for(i=0 ; i<Counter ; i++);
		xPLLADFC	= 0xEF;

		STA = 0;
		for(i=0 ; i<0x1000 ; i++)
		{
			if(xPLLLD & 0x40)
			{
				STA = 1;
				break;
			}
		}

		if(STA)	break;
	}

	xRXRFPD	= 0xF7;
	xRXRFPU	= 0xFF;
	xTXRFPD	= 0xFF;
	xTXRFPU	= 0xFF;
}



void ZHAL_CHANNEL_SET_CHIP92_XTAL16(UINT8 CH)
{
	UINT16		Counter;
	UINT8		STA;
	UINT16		i;
	UINT8		F3, F4;

	xRXRFPD	= 0x00;
	xRXRFPU	= 0xFF;
	xTXRFPD	= 0x00;
	xTXRFPU	= 0xFF;

	switch(CH) 
	{
		case 11 	: F3 = 0x06; F4 = 0x40;	 xPLLADIV = (xPLLADIV & 0x30) | 0x02; break;
		case 12 	: F3 = 0x0C; F4 = 0x80;	 xPLLADIV = (xPLLADIV & 0x30) | 0x02; break;
		case 13 	: F3 = 0x12; F4 = 0xC0;	 xPLLADIV = (xPLLADIV & 0x30) | 0x02; break;
		case 14 	: F3 = 0x19; F4 = 0x00;	 xPLLADIV = (xPLLADIV & 0x30) | 0x02; break;
		case 15 	: F3 = 0xBB; F4 = 0x40;	 xPLLADIV = (xPLLADIV & 0x30) | 0x03; break;
		case 16 	: F3 = 0xC1; F4 = 0x80;	 xPLLADIV = (xPLLADIV & 0x30) | 0x03; break;
		case 17 	: F3 = 0xC7; F4 = 0xC0;	 xPLLADIV = (xPLLADIV & 0x30) | 0x03; break;
		case 18 	: F3 = 0x32; F4 = 0x00;	 xPLLADIV = (xPLLADIV & 0x30) | 0x02; break;
		case 19 	: F3 = 0x38; F4 = 0x40;	 xPLLADIV = (xPLLADIV & 0x30) | 0x02; break;
		case 20 	: F3 = 0x3E; F4 = 0x80;	 xPLLADIV = (xPLLADIV & 0x30) | 0x02; break;
		case 21 	: F3 = 0x44; F4 = 0xC0;	 xPLLADIV = (xPLLADIV & 0x30) | 0x02; break;
		case 22 	: F3 = 0x4B; F4 = 0x00;	 xPLLADIV = (xPLLADIV & 0x30) | 0x02; break;
		case 23 	: F3 = 0xED; F4 = 0x40;	 xPLLADIV = (xPLLADIV & 0x30) | 0x03; break;
		case 24 	: F3 = 0xF3; F4 = 0x80;	 xPLLADIV = (xPLLADIV & 0x30) | 0x03; break;
		case 25 	: F3 = 0xF9; F4 = 0xC0;	 xPLLADIV = (xPLLADIV & 0x30) | 0x03; break;
		case 26 	: F3 = 0x00; F4 = 0x00;	 xPLLADIV = (xPLLADIV & 0x30) | 0x03; break;
		default	: F3 = 0x38; F4 = 0x40;	 xPLLADIV = (xPLLADIV & 0x30) | 0x02; break;
	}

	switch (CH) 
	{
		case 26 	: xPLLCP	= 0x3B;		break;
		default 	: xPLLCP 	= 0x32;		break;
	}
	
	xPLLRDIV	= (xPLLRDIV & 0x01);
	xPLLFRAC3	= F3;
	xPLLFRAC4	= F4;

	Counter = 0;
	while(1)
	{	
		Counter += 100;
		xPLLADFC	= 0xEF;
		for(i=0 ; i<Counter ; i++);
		xPLLADFC	= 0xEF;

		STA = 0;
		for(i=0 ; i<0x1000 ; i++)
		{
			if(xPLLLD & 0x40)
			{
				STA = 1;
				break;
			}
		}

		if(STA)	break;
	}

	xRXRFPD	= 0xF7;
	xRXRFPU	= 0xFF;
	xTXRFPD	= 0xFF;
	xTXRFPU	= 0xFF;
}


void ZHAL_CHANNEL_SET(UINT8 CH)
{
	if(xCHIPID == 0x91)
	{
		if(Mode_19MHz)
				ZHAL_CHANNEL_SET_CHIP91_XTAL19(CH);
		else		ZHAL_CHANNEL_SET_CHIP91_XTAL16(CH);
	}
	else
	{
		if(Mode_19MHz)
				ZHAL_CHANNEL_SET_CHIP92_XTAL19(CH);
		else		ZHAL_CHANNEL_SET_CHIP92_XTAL16(CH);
	}
}



void ZHAL_3V_LOGIC_INIT()
{	
	xPDM	= 0x00;
	xPDCON	= 0xE8;
	xRCOSC1= 0x3F;
	xRCOSC2= 0xF4;
	xRTDLY	= 0x02;
	xRTCON	= 0x80;
	xRTINT1	= 0x00;
	xRTINT0	= 0x08;
	xCKPLL	= 0xC2;
}


void ZHAL_MODEM_INIT_CHIP91(UINT8 XTAL19)
{
	UINT8	Tmp;
	
	xTDCNF3 = 0x7F;
	
	xAGCCNF3 = 0xFF;
	xAGCCNF5 = 0xE1;
	xAGCCNF8 = 0xA2;
	xAGCCNF10 = 0x69;
	xAGCCNF11 = 0xA2;
	
	xAGCCNF17 = 0xD7;
	xAGCCNF18 = 0xD7;
	xAGCCNF19 = 0xEF;
	xAGCCNF22 = 0xF7;
	xAGCCNF23 = 0x77;
	xAGCCNF24 = 0x88;
	xAGCCNF26 = 0x3F;

	xTST2 = 0xFF;
	xTST13 = 0x00;
	xTST15 = 0x00;

	xAGCSTS1 = 0xDF;
	xMONCON0 = 0x9E;

	xPLLADFC = 0x6C;
	xPLLLD = 0x01;
	xPLLCP = 0x22;
	xPLLVCO = 0x80;
	xPLLVC = 0xA8;
	xPLLDIV = 0x5A;
	xPLLBUF = 0x4F;

	xRXLNA = 0x12;
	xRXMIX = 0x50;
	xRXIP2I = 0x22;
	xRXIP2Q = 0x28;
	xRXBBAMP = 0xE8;
	xRXRSSI = 0x4B;
	xCTLVGA2 = 0xF8;
	xPLLLF1 = 0x04;
	xPLLLF2 = 0x8A;
	xPLLLF3 = 0x62;
	xVRXLPF = 0xE9;
		
	xTXPA = 0x9F;
	xTXDA = 0xFF;
	xTXMIX = 0x6F;
	xTXLPF = 0x12;
	xBIAS = 0x34;
	xSADCCON = 0x30;
	
	xSWRST = 0xBF;
	xRFCONCNF 	= 0xFD;

	xPLLPD  	= 0xFF;	// Release PLL Power-down
	xPLLPU	= 0xFF;	// Release PLL Power-up
	xRXRFPD = 0xFF;	// Release RF RX-path Power-down
	xRXRFPU = 0xFF;	// Release RF RX-path Power-up
	xTXRFPD	= 0xFF;	// Release RF TX-path Power-down
	xTXRFPU 	= 0xFF;	// Release RF TX-path Power-up
	xPCMD1  = 0x84;	// Release PHY TX/RX-path off
		
	if(XTAL19)		// 19.2 MHz PLL
	{
		xPLLADIV = 0x01;
		xPLLBDIV = 0x06;
		xPLLFRAC3 = 0x2E;
		xPLLFRAC4 = 0xE0;
	}

	xCTLVGA = 0x03;	
	xDCCCNF = 0x6C;			// Step 1 : Digital DCC Config
	xDCCCON = 0xC5;             	// Step 2 : Digital DCC Calibration 角青 夸没
	SetDelay(1,20000);		// Step 3 : Calibration Delay 汲沥, 
	xDCCCON = 0xC9;			// Step 4 : Final Set
	
	xINTCON = 0xFB;	// 1111_1011
	xPCMD0 &= 0x7F;	// bit[7]=0
	xPCMD0 &= 0xBF;	// bit[6]=0

	while(1)
	{
		Tmp = xINTSTS;
		if( (Tmp & 0x0F)==0x0E)
		{	
			Tmp = xINTIDX;
			EXIF &= ~0x10;
			break;
		}
	}
	
	xINTCON = 0xFA;		// 1111_1010. RxStart=0, Modem-On=0	
}




void ZHAL_MODEM_INIT_CHIP92(UINT8 XTAL19)
{
	UINT8	Tmp;
	
	xRFCONCNF 	= 0xFD;
	xCORCNF0	= 0xC0;
	xTDCNF3 	= 0x7F;

	xTDCNF2		= 0xFF;

	// REG V1.42
	xAGCCNF0 = 0xC2;
	xAGCCNF1 = 0x81;
	xAGCCNF3 = 0xFF;
	xAGCCNF5 = 0xDE;
	xAGCCNF6 = 0xD9;
	xAGCCNF7 = 0x83;	
	xAGCCNF8 = 0x8B;	
	xAGCCNF10 = 0xE0;
	xAGCCNF11 = 0x20;
	xAGCCNF15 = 0xCE;
	xAGCCNF16 = 0xD8;
	xAGCCNF17 = 0xE7;
	xAGCCNF18 = 0xE7;
	xAGCCNF19 = 0xEC;
	xAGCCNF22 = 0xF7;
	xAGCCNF23 = 0x77;
	xAGCCNF24 = 0x88;
	xAGCCNF26 = 0x3F;
	//	
	
	// RF Setting
	xPLLADFC = 0x6F;
	xPLLLD 	= 0x0A;
	xPLLCP 	= 0x32;
	xPLLVC 	= 0xE8;
	xPLLDIV 	= 0xFA;	
	xPLLBUF 	= 0x7F;
	xRXLNA 	= 0x12;
	xRXMIX 	= 0x70;
	xRXIP2I 	= 0x12;
	xRXIP2Q 	= 0x2A;
	xRXBBAMP = 0xD8;
	xRXRSSI = 0x4F;
	xCTLVGA = 0x00;
	xPLLLF1 	= 0x01;
	xPLLLF2 	= 0x9F;
	xPLLLF3 	= 0x78;
	xVRXLPF = 0xE0;	
	xTXPA 	= 0x9F;
	xTXDA 	= 0xFF;
	xTXMIX	= 0x6F;
	xTXLPF	= 0x12;		
	xBIAS 	= 0x11; 		//
	xSADCCON	= 0x30; 	//

	xRXRFPD = 0xF7;
	xRXRFPU = 0xFF;	// Release RF RX-path Power-up
	xPCMD0 &= 0x7F;

	if(XTAL19)		// 19.2 MHz PLL
	{
		xPLLADIV = 0x01;
		xPLLBDIV = 0x06;
		xPLLFRAC3 = 0x2E;
		xPLLFRAC4 = 0xE0;
	}	

	xPLLPD  	= 0xFF;	// Release PLL Power-down
	xPLLPU	= 0xFF;	// Release PLL Power-up
	xRXRFPD = 0xF7;	// Release RF RX-path Power-down
	xRXRFPU = 0xFF;	// Release RF RX-path Power-up
	xTXRFPD	= 0xFF;	// Release RF TX-path Power-down
	xTXRFPU 	= 0xFF;	// Release RF TX-path Power-up
	xPCMD1  = 0x84;	// Release PHY TX/RX-path off		

	// Digital DCC	
	xCLKON0 = 0xC2;	
	xRXRFPD = 0xF7;
	xRXRFPU = 0xFF;		
	xDCCCNF = 0x1C;
	xRXVGA = 0x06;
	xCTLVGA = 0x00;		// Analog DCC disable
	xDCCCON = 0xC5;		// Full Cal.	
	while(xDCCCON & 0x04);
	xCLKON0 = 0xFF;
	xDCCCNF = 0x08;
	xDCCCON = 0xC9;		// Tracking ON
	xRXRFPU = 0x00;
	//

	xINTCON = 0xFB;	// 1111_1011
	xPCMD0 &= 0x7F;	// bit[7]=0
	xPCMD0 &= 0xBF;	// bit[6]=0

	while(1)
	{
		Tmp = xINTSTS;
		if( (Tmp & 0x0F)==0x0E)
		{
	
			Tmp = xINTIDX;
			EXIF &= ~0x10;
			break;
		}