📄 mcu.h
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/*******************************************************************************
- Chip : MG24500/55
- Author : RadioPulse Inc, 2007.
- Date : 2007-07-02
- Version : VER 1.0
*******************************************************************************/
//--------------------------
// 8051 base registers
//--------------------------
sfr P0 = 0x80;
sfr SP = 0x81;
sfr DPL = 0x82;
sfr DPH = 0x83;
sfr P0MSK = 0x84;
sfr P0SEL = 0x85;
sfr PCON = 0x87;
sfr TCON = 0x88;
sfr TMOD = 0x89;
sfr TL0 = 0x8A;
sfr TL1 = 0x8B;
sfr TH0 = 0x8C;
sfr TH1 = 0x8D;
sfr P1 = 0x90;
sfr EXIF = 0x91;
sfr FBANK = 0xA1;
sfr AUXR1 = 0xA2;
sfr IE = 0xA8;
sfr T23CON = 0xA9;
sfr TH2 = 0xAA;
sfr TH3 = 0xAB;
sfr TL2 = 0xAC;
sfr TL3 = 0xAD;
sfr P3 = 0xB0;
sfr P0OEN = 0xB1;
sfr P1OEN = 0xB2;
sfr P3OEN = 0xB4;
sfr IP = 0xB8;
sfr P0REN = 0xB9;
sfr P1REN = 0xBA;
sfr P3REN = 0xBC;
sfr T4CON = 0xBD;
sfr TL4 = 0xBE;
sfr TH4 = 0xBF;
sfr WCON = 0xC0;
sfr PSW = 0xD0;
sfr WDT = 0xD2;
sfr EICON = 0xD8;
sfr ACC = 0xE0;
sfr EIE = 0xE8;
sfr B = 0xF0;
sfr EIP = 0xF8;
//--------------------------
// bit accessable sfr
//--------------------------
// EIP - Extended Interrupt Priority
// = EIP^7;
sbit VCEIP = EIP^6;
sbit SPIIP = EIP^5;
sbit RTCIP = EIP^4; // realtime clock
sbit T3IP = EIP^3; // timer3
sbit AESIP = EIP^2; // ADC/DES interrupt priority
sbit T2IP = EIP^1;
sbit RFIP = EIP^0;
// B
// EIE - Extended Interrupt Enable
// = EIE^7;
sbit VCEIE = EIE^6;
// = EIE^5;
sbit SPIIE = EIE^5;
sbit RTCIE = EIE^4; // realtime clock interrupt
sbit T3IE = EIE^3; // timer3 interrupt
sbit AESIE = EIE^2; // AES interrupt
sbit T2IE = EIE^1; // timer2 interrupt
sbit RFIE = EIE^0; // RF transmit/receive interrupt
// ACC
// EICON
// = EICON^7;
// = EICON^6;
// = EICON^5;
// = EICON^4;
sbit RTCIF = EICON^3;
// = EICON^2;
// = EICON^1;
// = EICON^0;
// PSW
sbit CY = PSW^7;
sbit AC = PSW^6;
sbit F0 = PSW^5;
sbit RS1 = PSW^4;
sbit RS0 = PSW^3;
sbit OV = PSW^2;
sbit F1 = PSW^1;
sbit PF = PSW^0; // Parity Flag
// WCON
// = WCON^7;
// = WCON^6;
// = WCON^5;
// = WCON^4;
// = WCON^3;
sbit ISPMODE= WCON^2;
sbit ENROM = WCON^1;
sbit CW = WCON^0;
// IP
// = IP^7;
sbit PS1 = IP^6;
// = IP^5;
sbit PS0 = IP^4;
sbit PT1 = IP^3;
sbit PX1 = IP^2;
sbit PT0 = IP^1;
sbit PX0 = IP^0;
// P3
sbit P3_7 = P3^7;
sbit P3_6 = P3^6;
sbit P3_5 = P3^5;
sbit P3_4 = P3^4;
sbit P3_3 = P3^3;
sbit P3_2 = P3^2;
sbit P3_1 = P3^1;
sbit P3_0 = P3^0;
// IE
sbit EA = IE^7; // interrupt enable
sbit ES1 = IE^6; // serial1 interrupt
// = IE^5;
sbit ES0 = IE^4; // serial0 interrupt
sbit ET1 = IE^3; // timer1 interrupt
sbit EX1 = IE^2; // ext1 interrupt
sbit ET0 = IE^1; // timer0 interrupt
sbit EX0 = IE^0; // ext0 interrupt
// P1
sbit P1_7 = P1^7;
sbit P1_6 = P1^6;
sbit P1_5 = P1^5;
sbit P1_4 = P1^4;
sbit P1_3 = P1^3;
sbit P1_2 = P1^2;
sbit P1_1 = P1^1;
sbit P1_0 = P1^0;
// TCON
sbit TF1 = TCON^7;
sbit TR1 = TCON^6;
sbit TF0 = TCON^5;
sbit TR0 = TCON^4;
sbit IE1 = TCON^3;
sbit IT1 = TCON^2;
sbit IE0 = TCON^1;
sbit IT0 = TCON^0;
// P0
sbit P0_7 = P0^7;
sbit P0_6 = P0^6;
sbit P0_5 = P0^5;
sbit P0_4 = P0^4;
sbit P0_3 = P0^3;
sbit P0_2 = P0^2;
sbit P0_1 = P0^1;
sbit P0_0 = P0^0;
//----------------------------------------------------
// MAC TX FIFO Control
//----------------------------------------------------
#define xMTFCPUSH XBYTE[0x2000]
#define xMTFCWP XBYTE[0x2001]
#define xMTFCRP XBYTE[0x2002]
#define xMTFCCTL XBYTE[0x2003]
#define xMTFCSTA XBYTE[0x2004]
#define xMTFCSIZE XBYTE[0x2005]
#define xMTFCROOM XBYTE[0x2006]
#define xMTFCSBASE XBYTE[0x2007]
#define xMTFCSLEN XBYTE[0x2008]
#define xAACKFC0 XBYTE[0x2009]
#define xAACKFC1 XBYTE[0x200A]
#define xAACKDSN XBYTE[0x200B]
#define xAACKSTA XBYTE[0x200C]
//----------------------------------------------------
// MAC RX FIFO Control
//----------------------------------------------------
#define xMRFCPOP XBYTE[0x2080]
#define xMRFCWP XBYTE[0x2081]
#define xMRFCRP XBYTE[0x2082]
#define xMRFCCTL XBYTE[0x2083]
#define xMRFCSTA XBYTE[0x2084]
#define xMRFCSIZE XBYTE[0x2085]
#define xMRFCROOM XBYTE[0x2086]
#define xMRFCSBASE XBYTE[0x2087]
#define xMRFCSLEN XBYTE[0x2088]
#define xFDSCPOPH XBYTE[0x2089]
#define xFDSCPOPL XBYTE[0x208A]
#define xFDSCSTA XBYTE[0x208B]
//----------------------------------------------------
// FFLT Control (1)
//----------------------------------------------------
#define xFFLT0SEQ XBYTE[0x20C0]
#define xFFLT1SEQ XBYTE[0x20C1]
#define xFFLT2SEQ XBYTE[0x20C2]
#define xFFLT3SEQ XBYTE[0x20C3]
#define xFFLT4SEQ XBYTE[0x20C4]
#define xFFLT5SEQ XBYTE[0x20C5]
#define xFFLT6SEQ XBYTE[0x20C6]
#define xFFLT7SEQ XBYTE[0x20C7]
#define xFFLT0AND XBYTE[0x20C8]
#define xFFLT1AND XBYTE[0x20C9]
#define xFFLT2AND XBYTE[0x20CA]
#define xFFLT3AND XBYTE[0x20CB]
#define xFFLT4AND XBYTE[0x20CC]
#define xFFLT5AND XBYTE[0x20CD]
#define xFFLT6AND XBYTE[0x20CE]
#define xFFLT7AND XBYTE[0x20CF]
//----------------------------------------------------
// FFLT Control (2)
//----------------------------------------------------
#define xFFLT0OR XBYTE[0x20D0]
#define xFFLT1OR XBYTE[0x20D1]
#define xFFLT2OR XBYTE[0x20D2]
#define xFFLT3OR XBYTE[0x20D3]
#define xFFLT4OR XBYTE[0x20D4]
#define xFFLT5OR XBYTE[0x20D5]
#define xFFLT6OR XBYTE[0x20D6]
#define xFFLT7OR XBYTE[0x20D7]
#define xFFLT0VAL XBYTE[0x20D8]
#define xFFLT1VAL XBYTE[0x20D9]
#define xFFLT2VAL XBYTE[0x20DA]
#define xFFLT3VAL XBYTE[0x20DB]
#define xFFLT4VAL XBYTE[0x20DC]
#define xFFLT5VAL XBYTE[0x20DD]
#define xFFLT6VAL XBYTE[0x20DE]
#define xFFLT7VAL XBYTE[0x20DF]
//----------------------------------------------------
// FFLT Control (3)
//----------------------------------------------------
#define xFFLTRES XBYTE[0x20E0]
#define xFFLTENA XBYTE[0x20E1]
#define xFFLTFLD XBYTE[0x20E2]
//----------------------------------------------------
// MAC Control : 0x2100 ~ 0x2195
//----------------------------------------------------
#define xKEY0(n) XBYTE[0x2100+n] // MSB = 0x190F
#define xRXNONCE(n) XBYTE[0x2110+n] // MSB = 0x191C
#define xSAESBUF(n) XBYTE[0x2120+n] // ?????
#define xKEY1(n) XBYTE[0x2130+n] // MSB = 0x193F
#define xTXNONCE(n) XBYTE[0x2140+n] // MSB = 0x194C
#define xEXTADDR(n) XBYTE[0x2150+n] // MSB = 0x1957
#define xPANID(n) XBYTE[0x2158+n] // MSB = 0x1959
#define xSHORTADDR(n) XBYTE[0x215A+n] // MSB = 0x195B
//-----------------------------
// MAC STATUS
//-----------------------------
// bit[7] : enc/dec :: default= 0
// bit[6] : tx_busy :: default= 0
// bit[5] : rx_busy :: default= 0
// bit[4] : rsv :: default= 0
// bit[3] : decode_ok :: default= 1
// bit[2] ; enc_done :: default= 0
// bit[1] : dec_done :: default= 0
// bit[0] : crc_ok :: default= 1
#define xMACSTS XBYTE[0x2180] // xMAC_STA
//-----------------------------
//-----------------------------
// MAC SAES
// bit[7:1] : reserved
// bit[0] : SAES
//-----------------------------
#define xMACSAES XBYTE[0x218E] // xMAC_SAES
//-----------------------------
// MAC MAIN
//-----------------------------
// bit[7] : rst_fifo
// bit[6] : rst_tsm
// bit[5] : rst_rsm
// bit[4] : rst_aes
// bit[3:0] : rsv
#define xMACRST XBYTE[0x2190] // xMAC_MAIN
//-----------------------------
//-----------------------------
// MAC MODEM
//-----------------------------
// bit[7:5] : rsv :: default=0
// bit[4] : prevent_ack_packet :: default=0
// bit[3] : pan_coordinator :: default=0
// bit[2] ; addr_decode :: default=1
// bit[1] : auto_crc :: default=1
// bit[0] : auto_ack :: default=0
#define xMACCTRL XBYTE[0x2191] // xMACCTRL
//-----------------------------
#define xMACDSN XBYTE[0x2192] // xMAC_DSN
//-----------------------------
// MAC SEC
//-----------------------------
// bit[7] : sa_keysel
// bit[6] : tx_keysel
// bit[5] : rx_keysel
// bit[4:2] : sec_m[2:0]
// bit[1:0] : sec_mode[1:0]
#define xMACSEC XBYTE[0x2193] // xMAC_SEC
//-----------------------------
#define xTXAL XBYTE[0x2194] // bit[7] : rsv // xMAC_TXL
#define xRXAL XBYTE[0x2195] // bit[7] : rsv // xMAC_RXL
//----------------------------------------------------
// MAC TX FIFO : 0x2300 ~ 0x23FF
//----------------------------------------------------
#define xMTxFIFO(n) XBYTE[0x2300+n]
//----------------------------------------------------
// MAC RX FIFO : 0x2400 ~ 0x24FF
//----------------------------------------------------
#define xMRxFIFO(n) XBYTE[0x2400+n]
//----------------------------------------------------
// UART0
//----------------------------------------------------
#define xU0_RBR XBYTE[0x2500]
#define xU0_THR XBYTE[0x2500]
#define xU0_DLL XBYTE[0x2500]
#define xU0_IER XBYTE[0x2501]
#define xU0_DLM XBYTE[0x2501]
#define xU0_IIR XBYTE[0x2502] // Read Only
#define xU0_FCR XBYTE[0x2502] // Write Only
#define xU0_LCR XBYTE[0x2503]
#define xU0_MCR XBYTE[0x2504]
#define xU0_LSR XBYTE[0x2505]
#define xU0_MSR XBYTE[0x2506]
#define xU0_PENA XBYTE[0x2507]
//----------------------------------------------------
// UART1
//----------------------------------------------------
#define xU1_RBR XBYTE[0x2510]
#define xU1_THR XBYTE[0x2510]
#define xU1_DLL XBYTE[0x2510]
#define xU1_IER XBYTE[0x2511]
#define xU1_DLM XBYTE[0x2511]
#define xU1_IIR XBYTE[0x2512] // Read Only
#define xU1_FCR XBYTE[0x2512] // Write Only
#define xU1_LCR XBYTE[0x2513]
#define xU1_MCR XBYTE[0x2514]
#define xU1_LSR XBYTE[0x2515]
#define xU1_MSR XBYTE[0x2516]
#define xU1_PENA XBYTE[0x2517]
//----------------------------------------------------
// I2STX
//----------------------------------------------------
#define xSTXDATL3 XBYTE[0x2520]
#define xSTXDATL2 XBYTE[0x2521]
#define xSTXDATL1 XBYTE[0x2522]
#define xSTXDATL0 XBYTE[0x2523]
#define xSTXDATR3 XBYTE[0x2524]
#define xSTXDATR2 XBYTE[0x2525]
#define xSTXDATR1 XBYTE[0x2526]
#define xSTXDATR0 XBYTE[0x2527]
#define xSTXAIC XBYTE[0x2528]
//------------------------
// STXAIC
//------------------------
// [7] : 1=Master, 0=Slave
// [6:5] : 0=I2S, 1=LFT, 2=RHT, 3=DSP
// [4:3] : Word Length. 0=16Byte, 1=20Byte, 2=24Byte, 3=32Byte
// [2] : LRSWAP. 0=Left, 1=Right
// [1] : FRAMEP. 0=Sync, 1=Delay
// [0] : BCP. 0=Normal, 1=Invert
//------------------------
#define xSTXSTS XBYTE[0x2529]
#define xSTXSDIV XBYTE[0x252A]
#define xSTXMDIV XBYTE[0x252B]
#define xSTXBDIV XBYTE[0x252C]
#define xSTXMODE XBYTE[0x252D]
//------------------------
// STXMODE
//------------------------
// [7] : CSHR
// [6] : MPOL
// [5] : BPOL
// [4] : B16
// [3] : POP
// [2:1] : 0=BLK, 1=MRT, 2=MLT, 3=STR
// [0] : CLKENA
//------------------------
#define xSTXINTENA XBYTE[0x252E]
#define x252F XBYTE[0x252F]
//----------------------------------------------------
// I2SRX
//----------------------------------------------------
#define xSRXDATL3 XBYTE[0x2530]
#define xSRXDATL2 XBYTE[0x2531]
#define xSRXDATL1 XBYTE[0x2532]
#define xSRXDATL0 XBYTE[0x2533]
#define xSRXDATR3 XBYTE[0x2534]
#define xSRXDATR2 XBYTE[0x2535]
#define xSRXDATR1 XBYTE[0x2536]
#define xSRXDATR0 XBYTE[0x2537]
#define xSRXAIC XBYTE[0x2538]
//------------------------
// SRXAIC
//------------------------
// [7] : 1=Master, 0=Slave
// [6:5] : 0=I2S, 1=LFT, 2=RHT, 3=DSP
// [4:3] : Word Length. 0=16Byte, 1=20Byte, 2=24Byte, 3=32Byte
// [2] : LRSWAP. 0=Left, 1=Right
// [1] : FRAMEP. 0=Sync, 1=Delay
// [0] : BCP. 0=Normal, 1=Invert
//------------------------
#define xSRXSTS XBYTE[0x2539]
#define xSRXSDIV XBYTE[0x253A]
#define xSRXMDIV XBYTE[0x253B]
#define xSRXBDIV XBYTE[0x253C]
#define xSRXMODE XBYTE[0x253D]
//------------------------
// SRXMODE
//------------------------
// [7] : CSHR
// [6] : MPOL
// [5] : BPOL
// [4] : B16
// [3] : POP
// [2:1] : 0=BLK, 1=MRT, 2=MLT, 3=STR
// [0] : CLKENA
//------------------------
#define xSRXINTENA XBYTE[0x253E]
#define xSRXLPB XBYTE[0x253F]
//----------------------------------------------------
// SPI
//----------------------------------------------------
#define xSPCR XBYTE[0x2540]
#define xSPSR XBYTE[0x2541]
#define xSPDR XBYTE[0x2542]
#define xSPER XBYTE[0x2543]
//----------------------------------------------------
// RNG
//----------------------------------------------------
#define xRNGD3 XBYTE[0x2550]
#define xRNGD2 XBYTE[0x2551]
#define xRNGD1 XBYTE[0x2552]
#define xRNGD0 XBYTE[0x2553]
#define xSEED3 XBYTE[0x2554]
#define xSEED2 XBYTE[0x2555]
#define xSEED1 XBYTE[0x2556]
#define xSEED0 XBYTE[0x2557]
#define xRNGC XBYTE[0x2558]
//----------------------------------------------------
// QUAD
//----------------------------------------------------
#define xUDX XBYTE[0x2560]
#define xCNTX XBYTE[0x2561]
#define xUDY XBYTE[0x2562]
#define xCNTY XBYTE[0x2563]
#define xUDZ XBYTE[0x2564]
#define xCNTZ XBYTE[0x2565]
#define xQCTL XBYTE[0x2566]
//----------------------------------------------------
// VFIFO
//----------------------------------------------------
#define xVTxFIFO(n) XBYTE[0x2600+n] // 0x2600 ~ 0x267F
#define xVRxFIFO(n) XBYTE[0x2680+n] // 0x2680 ~ 0x26FF
//----------------------------------------------------
// FCNTL Control
//----------------------------------------------------
#define xFCN_CMD XBYTE[0x2700]
#define xFCN_CSUM XBYTE[0x2701]
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