📄 mstar.c
字号:
#define MST_HPeriod_UINT MST_CLOCK_MHZ*16
Bool mStar_SetPanelTiming(void)
{ DWORD factor;
WORD dclk;
WORD sclk;
WORD height;
WORD dstHTotal;
WORD hPeriod;
// for getting more accurate output htotal
if (SrcHPeriod>511) // avoid overflow
hPeriod=SrcHPeriod*16;
else
{ sclk=GetVSyncTime()*3;
mStar_WriteByte(HSPRD_H, IHDM_B); // enable 16 line line to calculate hsync period.
Delay1ms(sclk);
hPeriod=mStar_ReadWord(HSPRD_H)&0x1FFF;
if (abs(hPeriod/16-SrcHPeriod)>5) // sail add for CPTEA03 setPanelTimg fail 20040622
hPeriod=SrcHPeriod*16;
mStar_WriteByte(HSPRD_H, 0);
Delay1ms(sclk);
}
#if EnableVideo656Port
//Vick auto switch option
if ((SrcInputType == Input_656Video)&&SyncLossState())
hPeriod=SrcHPeriod*16;
#endif
// calculate input timing dot clock for comparing with output dot clock
sclk=0;
if (mStar_ReadWord(SPRHDC_H)<PanelWidth || mStar_ReadWord(SPRVDC_H)<PanelHeight)
{
sclk=((DWORD)UserPrefHTotal*MST_HPeriod_UINT)/((DWORD)hPeriod*1000);
}
//printData("input sclk %d", sclk);
height=mStar_ReadWord(SPRVDC_H);
if (SrcFlags&bInterlaceMode)
height/=2;
dstHTotal=PanelMinHTotal;
#if FixDClk // Fixed output dclk method: output clock will be fixed no matter what input timing is
{ // according to output clock to calculate output htotal
dclk=OutDClk1;
dstHTotal=((float)hPeriod*dclk*(height-1)*1000ul)/((float)(PanelHeight-1)*MST_HPeriod_UINT);
//printData("dclk1 output htotal %d", dstHTotal);
if (dstHTotal<PanelMinHTotal) // if input htotal is samll than panel htotal, then set to another dclk
{ dclk=OutDClk2;
dstHTotal=((float)hPeriod*dclk*(height-1)*1000ul)/((float)(PanelHeight-1)*MST_HPeriod_UINT);
//printData("dclk2 output htotal %d", dstHTotal);
}
dstHTotal&=0xFFFE; // make output htotal as even
// if the htotal is out of panel htotal, then use the panel minimum htotal
if (dstHTotal<PanelMinHTotal || dstHTotal>PanelMaxHTotal)
dstHTotal=PanelMinHTotal;
}
#endif
mStar_WriteWord(DEHST_H, PanelHStart);
if (sclk)
{ // in expansion mode, chip will assume output clock is faster than input clock,
// if input clock is faster than output clock, must make output clock faster than input clock
#if PanelTB141LA1
if(SrcModeIndex==0) //tony for Panle OCLK outof range
{
dstHTotal*=5;
dstHTotal/=6;
}
/*
if(SrcModeIndex==14) //tony for Panle OCLK outof range// Yurian modify @ Nov-16-2004
{
dstHTotal*=17;
dstHTotal/=16;
}
*/
#elif (PanelCPTXG08|PanelCPTXP02)
if(SrcModeIndex==0) //tony for Panle OCLK outof range
{
dstHTotal*=6;
dstHTotal/=7;
}
#elif PanelHstSX84
if(SrcModeIndex==0)
{
dstHTotal*=25;
dstHTotal/=28;
}
#elif PanelCPTXG09
if(SrcModeIndex==0)
{
dstHTotal*=21;
dstHTotal/=22;
}
#elif PanelCPT154WA01
if(SrcModeIndex==2)
{
dstHTotal*=16;
dstHTotal/=17;
}
else if(SrcModeIndex==0)
{
dstHTotal*=8;
dstHTotal/=7;
mStar_WriteWord(DEHST_H, PanelHStart+9); // Hor. DE start
}
#elif PanelAU150XN07|PanelHITACHI15)
if(SrcModeIndex==0||SrcModeIndex==2)
{
dstHTotal*=16;
dstHTotal/=17;
}
if(SrcModeIndex==6||SrcModeIndex==8)
{
dstHTotal*=21;
dstHTotal/=20;
}
#elif PanelHanStarSXA1
if(SrcModeIndex==0)
{
dstHTotal*=17;
dstHTotal/=20;
}
#elif PanelHannStar150MX15
if(SrcModeIndex==0)
{
dstHTotal*=17;
dstHTotal/=18;
}
#elif PanelHstSX84
if(SrcModeIndex==0)
{
dstHTotal*=29; //7
dstHTotal/=28; //8
mStar_WriteByte(OSCTRL, 0x30);
}
else
mStar_WriteByte(OSCTRL, (PanelDClkDelay<<4)|(OCLK_B&PanelInvDClk)|(OVS_B&PanelInvVSync)|(OHS_B&PanelInvHSync));
#endif
factor=((float)dstHTotal*(PanelHeight-1)*MST_HPeriod_UINT)/((DWORD)hPeriod*(height-1)); // output dclk
dclk=(factor+500)/1000;
#if DEBUG_ENABLE
printData("output dclk %d", dclk);
#endif
#if OutRange_Display
if(SrcModeIndex>43||(SrcModeIndex<40 && SrcModeIndex!=36&&SrcModeIndex!=0))
#endif
if (dclk>PanelMaxDCLK) // if ouput clock is out of panel, then enable unsupported flag
{ SrcFlags|=bUnsupportMode;
return FALSE;
}
#if ChipID==ChipNone
if (dclk<(sclk+3))
{ // output clock is slow than input clock, so fast output clock
factor+=(sclk+3-dclk)*1000;
dstHTotal=((float)hPeriod*factor*(height-1))/((float)MST_HPeriod_UINT*(PanelHeight-1));
if (dstHTotal%4)
dstHTotal=(dstHTotal/4+1)*4;
}
#endif
}
{ // used for support frequency over 173MHz, and native mode
#if MSTMCU
#if DoubleSpeed
#define MPLL_Divider 7.5//15
#else
#define MPLL_Divider 15
#endif
#else
#define MPLL_Divider 15
#endif
if (sclk==0)
sclk=((DWORD)UserPrefHTotal*MST_HPeriod_UINT)/((DWORD)hPeriod*1000);
mStar_WriteByte(REGBK, REGBANKADC);
mStar_WriteByte(TESTEN, TSTEN_B);
if (SrcInputType!=Input_Digital)
{ if (sclk<20)
mStar_WriteByte(VCOCTRL, 0x05); // set VCO range
else if (sclk>140)
mStar_WriteByte(VCOCTRL, 0x35); // set VCO range
else
mStar_WriteByte(VCOCTRL, 0x15); // set VCO range
if (sclk>173)
mStar_WriteByte(TESTA3, 0xC0);
else
mStar_WriteByte(TESTA3, 0x00); //0x20 22/12/03
}
else
mStar_WriteByte(TESTA3, 0x00);
mStar_WriteByte(TESTEN, 0x00);
mStar_WriteByte(REGBK, REGBANKSCALER);
#define regByte dclk
regByte=mStar_ReadByte(ISCTRL);
if (sclk>165)
mStar_WriteByte(ISCTRL, regByte|SCKI_B);
else
mStar_WriteByte(ISCTRL, regByte&~SCKI_B);
#undef regByte
#if PanelLVDS
factor=((float)hPeriod*524288ul*MPLL_Divider*(height-1))/((float)dstHTotal*7*(PanelHeight-1)); // 2^23
#else
factor=((float)hPeriod*65536ul*MPLL_Divider*(height-1))/((float)dstHTotal*(PanelHeight-1)); // 2^20
#endif
#undef MPLL_Divider
}
#if (!PanelRSDS && !PanelDualPort)
factor/=2;
#endif
// program LPLL parameters to generate expected output dclk
mStar_WriteWord(LPLL_SET_M, factor&0xFFFF);
mStar_WriteByte(LPLL_SET_H, factor>>16);
mStar_WriteByte(ISELECT, mStar_ReadByte(ISELECT)&(~NIS_B));// enable lock input mode
mStar_ResetDClkPLL(); // reset output PLL to prevent PLL works abnormally
#if PanelTB141LA1//Max modify for Costdown_16AK_Audio_A_TB141LA1 @ Nov-10-2004
mStar_WriteByte(REGBK,REGBANKTCON);
mStar_WriteByte(IFCTRL, OuputFormatM);
mStar_WriteWord(GAVST_H, GPOA_VStartM);
if(SrcModeIndex==6||SrcModeIndex==7)//Yurian modify @ Nov-16-2004
{
mStar_WriteByte(GAVEND_L, 0x40);
mStar_WriteByte(GAVEND_H, 0x03);
}
else if(SrcModeIndex==8||SrcModeIndex==13)
{
mStar_WriteByte(GAVEND_L, 0x37);
mStar_WriteByte(GAVEND_H, 0x03);
}
else if(SrcModeIndex==9)
{
mStar_WriteByte(GAVEND_L, 0x1A);
mStar_WriteByte(GAVEND_H, 0x03);
}
else if(SrcModeIndex==19||SrcModeIndex==20)
{
mStar_WriteByte(GAVEND_L, 0x19);
mStar_WriteByte(GAVEND_H, 0x03);
}
else if(SrcModeIndex==11||SrcModeIndex==12||SrcModeIndex==14||SrcModeIndex==20)
{
mStar_WriteByte(GAVEND_L, 0x10);
mStar_WriteByte(GAVEND_H, 0x03);
}
else if(SrcModeIndex==2||SrcModeIndex==4)
{
mStar_WriteByte(GAVEND_L, 0x50);
mStar_WriteByte(GAVEND_H, 0x03);
}
else if(SrcModeIndex==1)
{
mStar_WriteByte(GAVEND_L, 0xAF);
mStar_WriteByte(GAVEND_H, 0x03);
}
else if(SrcModeIndex==0)
{
mStar_WriteByte(GAVEND_L, 0xD0);
mStar_WriteByte(GAVEND_H, 0x03);
}
else
mStar_WriteWord(GAVEND_H, GPOA_VEndM);
mStar_WriteByte(REGBK,REGBANKSCALER);
#endif
#if PanelHT17E13_100 //moson modify TSUM @ 20050706
mStar_WriteByte(REGBK,REGBANKTCON);
// mStar_WriteByte(IFCTRL, OuputFormatM);
mStar_WriteWord(GAVST_H, GPOA_VStartM);
if(SrcModeIndex==0)//moson modify @ 20050706
{
mStar_WriteByte(GAVEND_L, 0x11);
mStar_WriteByte(GAVEND_H, 0x05);
}
else if(SrcModeIndex==4)
{
mStar_WriteByte(GAVEND_L, 0x57);
mStar_WriteByte(GAVEND_H, 0x04);
}
else if(SrcModeIndex==6||SrcModeIndex==7)
{
mStar_WriteByte(GAVEND_L, 0x51);
mStar_WriteByte(GAVEND_H, 0x04);
}
else if(SrcModeIndex==8)
{
mStar_WriteByte(GAVEND_L, 0x48);
mStar_WriteByte(GAVEND_H, 0x04);
}
else if(SrcModeIndex==9)
{
mStar_WriteByte(GAVEND_L, 0x17);
mStar_WriteByte(GAVEND_H, 0x04);
}
else if(SrcModeIndex==2)
{
mStar_WriteByte(GAVEND_L, 0x6f);
mStar_WriteByte(GAVEND_H, 0x04);
}
else if(SrcModeIndex==11||SrcModeIndex==14)
{
mStar_WriteByte(GAVEND_L, 0x2c);
mStar_WriteByte(GAVEND_H, 0x04);
}
else if(SrcModeIndex==12||SrcModeIndex==17)
{
mStar_WriteByte(GAVEND_L, 0x21);
mStar_WriteByte(GAVEND_H, 0x04);
}
else if(SrcModeIndex==13)
{
mStar_WriteByte(GAVEND_L, 0x62);
mStar_WriteByte(GAVEND_H, 0x04);
}
else if(SrcModeIndex==34||SrcModeIndex==32)
{
mStar_WriteByte(GAVEND_L, 0x1a);
mStar_WriteByte(GAVEND_H, 0x04);
}
else
mStar_WriteWord(GAVEND_H, GPOA_VEndM);
mStar_WriteByte(REGBK,REGBANKSCALER);
#endif
#if PanelLGx08//PRV765_A_LG
ModeTrack();
#elif (PanelAUEN05|PanelAU150XN07|PanelCPT190EA03|PanelAUEG01|PanelAUEG01_v2)
ModeTrack(factor);
#endif
return TRUE;
}
//*******************************************************************
// Function Name: mStar_PowerUp
//
// Decscription: Power on chip from power down mode
//
// callee: mStar_WriteByte() in ms_rwreg.c
//
// caller: Power_PowerOnSystem() in power.c
//*******************************************************************
void mStar_PowerUp(void)
{ //mStar_WriteByte(TRISTATE, 0x00);
#if (PanelCPTXG08|PanelCPTEA03|PanelHstSX84|PanelHanStarSXA1|PanelHstSX84_F|PanelCPTXP02)
mStar_WriteByte(PLLCTRL2, BIT7); // power on master & output PLL
#else
mStar_WriteByte(PLLCTRL2, 0x00);
#endif
mStar_WriteByte(PDMD, 0|VDD2LOW);// power on chip from power down mode //2005-11-12 Update
#if ADC2Sets
mStar_WriteByte(REGBK, REGBANKADC);
mStar_WriteByte(TESTEN, TSTEN_B);
mStar_WriteByte(TESTA5, 0);
mStar_WriteByte(TESTA6, 0);
#if (!PanelAUEN05&&!PanelAUEG01&&!PanelAUEG01_v2)
mStar_WriteByte(TESTMOD, 0x10);//0x08);//0x40);
#endif
mStar_WriteByte(TESTEN, 0);
mStar_WriteByte(REGBK, REGBANKSCALER);
#endif
mStar_WriteByte(SWRST, GPR_B|ADCR_B); // reset graphic port RO register
mStar_WriteByte(SWRST, 0);
}
//*******************************************************************
// Function Name: mStar_PowerDown
//
// Decscription: Power down chip
//
// callee: mStar_WriteByte() in ms_rwreg.c
//
// caller: Power_PowerOffSystem() in power.c
//*******************************************************************
void mStar_PowerDown(void)
{ mStar_WriteByte(TRISTATE, 0xFF);// tri-state all output panel signal
#if ADC2Sets
{ BYTE regByte=0x9E;//OVRD_B|DPLBG_B|DMIBEX_B|PHD_B|DMUX_B;
mStar_WriteByte(PLLCTRL2, MP_PD_B|LP_PD_B);
if (SrcInputType==Input_Digital)
regByte=0x86;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -