hw_ili9320.c

RK27驱动

	Mcupanel_RegSet(0x0010, 0x17B0);		 // SAP, BT[3:0], AP, DSTB, SLP, STB
	Mcupanel_RegSet(0x0011, 0x0007);		 // DC1[2:0], DC0[2:0], VC[2:0]
	delay_nops(50);					 // Delay 50ms
	Mcupanel_RegSet(0x0012, 0x013c);		 // VREG1OUT voltage
	delay_nops(50);					 // Delay 50ms
	Mcupanel_RegSet(0x0013, 0x1400);		 // VDV[4:0] for VCOM amplitude
	Mcupanel_RegSet(0x0029, 0x0012);		 // VCM[4:0] for VCOMH
	delay_nops(50);

	Mcupanel_RegSet(0x0020, 0x0000);		 // GRAM horizontal Address
	Mcupanel_RegSet(0x0021, 0x0000);		 // GRAM Vertical Address

	// ----------- Adjust the Gamma	Curve ----------//
	Mcupanel_RegSet(0x0030, 0x0002);
	Mcupanel_RegSet(0x0031, 0x0606);
	Mcupanel_RegSet(0x0032, 0x0501);


	Mcupanel_RegSet(0x0035, 0x0206);
	Mcupanel_RegSet(0x0036, 0x0504);
	Mcupanel_RegSet(0x0037, 0x0707);
	Mcupanel_RegSet(0x0038, 0x0306);
	Mcupanel_RegSet(0x0039, 0x0007);

	Mcupanel_RegSet(0x003C, 0x0700);
	Mcupanel_RegSet(0x003D, 0x0700);

	//------------------ Set GRAM area ---------------//
	Mcupanel_RegSet(0x0050, 0x0000);		// Horizontal GRAM Start Address
	Mcupanel_RegSet(0x0051, 0x00EF);		// Horizontal GRAM End Address
	Mcupanel_RegSet(0x0052, 0x0000);		// Vertical GRAM Start Address
	Mcupanel_RegSet(0x0053, 0x013F);		// Vertical GRAM Start Address


	Mcupanel_RegSet(0x0060, 0x2700);		// Gate Scan Line
	Mcupanel_RegSet(0x0061, 0x0001);		// NDL,VLE, REV
	Mcupanel_RegSet(0x006A, 0x0000);		// set scrolling line

	//-------------- Partial Display Control ---------//
	Mcupanel_RegSet(0x0080, 0x0000);
	Mcupanel_RegSet(0x0081, 0x0000);
	Mcupanel_RegSet(0x0082, 0x0000);
	Mcupanel_RegSet(0x0083, 0x0000);
	Mcupanel_RegSet(0x0084, 0x0000);
	Mcupanel_RegSet(0x0085, 0x0000);

	//-------------- Panel Control -------------------//
	Mcupanel_RegSet(0x0090, 0x0010);
	Mcupanel_RegSet(0x0092, 0x0000);
	Mcupanel_RegSet(0x0093, 0x0003);
	Mcupanel_RegSet(0x0095, 0x0110);
	Mcupanel_RegSet(0x0097, 0x0000);
	Mcupanel_RegSet(0x0098, 0x0000);


	Mcupanel_RegSet(0x0007, 0x0173);		// 262K color and display ON
	Mcupanel_Command(0x0022);
#endif

//############################KGM529D01-1A##########################################
#if	(LCM_9320 == 8)


	delay_nops(10);
	//************* Start Initial Sequence **********//
	Mcupanel_RegSet(0x00, 0x0001);		// Start internal OSC.
	Mcupanel_RegSet(0x01, 0x0000); //0x0100);		// set SS and SM bit
	Mcupanel_RegSet(0x02, 0x0400);		// set 1 line inversion
	Mcupanel_RegSet(0x03, 0x10b8); //0x1038); //0x1028); //0x1038);		// set GRAM write direction and BGR=1.
	Mcupanel_RegSet(0x04, 0x0000);		// Resize register
	Mcupanel_RegSet(0x08, 0x0202);		// set the back porch and front porch
	Mcupanel_RegSet(0x09, 0x0000);		// set non-display area refresh cycle ISC[3:0]
	Mcupanel_RegSet(0x0A, 0x0000);		// FMARK function
	Mcupanel_RegSet(0x0C, 0x0000);		// RGB interface setting
	Mcupanel_RegSet(0x0D, 0x0000);		// Frame marker Position
	Mcupanel_RegSet(0x0F, 0x0000);		// RGB interface polarity

	//*************Power On sequence ****************//    WCOM(0x51, 0x00, 0xEF);
	Mcupanel_RegSet(0x10, 0x0000);                // SAP, BT[3:0], AP, DSTB, SLP, STB
	Mcupanel_RegSet(0x11, 0x0007);                // DC1[2:0], DC0[2:0], VC[2:0]
	Mcupanel_RegSet(0x12, 0x0000);                // VREG1OUT voltage
	Mcupanel_RegSet(0x13, 0x0000);                // VDV[4:0] for VCOM amplitude
	delay_nops(50);

	//*************Power On sequence ****************//    WCOM(0x51, 0x00, 0xEF);
	Mcupanel_RegSet(0x07, 0x0101);
	Mcupanel_RegSet(0x10, 0x10B0); //0000);     // SAP, BT[3:0], AP, DSTB, SLP, STB
	Mcupanel_RegSet(0x11, 0x0007);              // DC1[2:0], DC0[2:0], VC[2:0]
	delay_nops(50);
	Mcupanel_RegSet(0x07, 0x0001);
	Mcupanel_RegSet(0x12, 0x0139); //0000);     // VREG1OUT voltage
	delay_nops(50);
	Mcupanel_RegSet(0x13, 0x0c00); //0000);     // VDV[4:0] for VCOM amplitude
	Mcupanel_RegSet(0x29, 0x000a); //B);
	delay_nops(50);

	Mcupanel_RegSet(0x20, 0x0000);                // GRAM horizontal Address
	Mcupanel_RegSet(0x21, 0x0000);                // GRAM Vertical Address
	Mcupanel_RegSet(0x2B, 0x0020);		// Frame Rate and Color Control-----16M_EN, Dither, FR_SEL[1:0]

	Mcupanel_RegSet(0x30, 0x0002);
	Mcupanel_RegSet(0x31, 0x0606);
	Mcupanel_RegSet(0x32, 0x0501);


	Mcupanel_RegSet(0x35, 0x0206);
	Mcupanel_RegSet(0x36, 0x0504);
	Mcupanel_RegSet(0x37, 0x0707);
	Mcupanel_RegSet(0x38, 0x0306);
	Mcupanel_RegSet(0x39, 0x0007);

	Mcupanel_RegSet(0x3C, 0x0700);
	Mcupanel_RegSet(0x3D, 0x0700);

	// ---------- Window Address Area  ---------- //
	Mcupanel_RegSet(0x50, 0x0000);		// Horizontal GRAM Start Address-----HSA[7:0]
	Mcupanel_RegSet(0x51, 0x00EF);		// Horizontal GRAM End Address-----HEA[7:0]
	Mcupanel_RegSet(0x52, 0x0000);		// Vertical GRAM Start Address-----VSA[8:0]
	Mcupanel_RegSet(0x53, 0x013F);		// Vertical GRAM Start Address-----VEA[8:0]

	// ---------- Gate Scan Control  ---------- //
	Mcupanel_RegSet(0x60, 0x2700);		// GS, NL[5:0], SCN[5:0]
	Mcupanel_RegSet(0x61, 0x0001);		// NDL,VLE, REV
	Mcupanel_RegSet(0x6A, 0x0000);		// VL[8:0]

	// ---------- Partial Display Control  ---------- //
	Mcupanel_RegSet(0x80, 0x0000);		// Partial Image 1 Display Position-----PTDP0[8:0]
	Mcupanel_RegSet(0x81, 0x0000);		// Partial Image 1 Start Address-----PTSA0[8:0]
	Mcupanel_RegSet(0x82, 0x0000);		// Partial Image 1 End Address-----PTEA0[8:0]
	Mcupanel_RegSet(0x83, 0x0000);		// Partial Image 2 Display Position-----PTDP1[8:0]
	Mcupanel_RegSet(0x84, 0x0000);		// Partial Image 2 Start Address-----PTSA1[8:0]
	Mcupanel_RegSet(0x85, 0x0000);		// Partial Image 2 Start Address-----PTEA1[8:0]

	// ---------- Panel Interface Control  ---------- //
	Mcupanel_RegSet(0x90, 0x0013);		// Panel Interface Control 1-----DIVI[1:0], RTNI[4:0]
	Mcupanel_RegSet(0x92, 0x0000);		// Panel Interface Control 2-----NOWI[2:0]
	Mcupanel_RegSet(0x93, 0x0003);		// Panel Interface Control 3-----MCPI[2:0]
	Mcupanel_RegSet(0x95, 0x0110);		// Panel Interface Control 4-----DIVE[1:0], RTNE[5:0]
	Mcupanel_RegSet(0x97, 0x0000);		// Panel Interface Control 5-----NOWE[3:0]
	Mcupanel_RegSet(0x98, 0x0000);		// Panel Interface Control 6-----MCPE[2:0]

	Mcupanel_RegSet(0x07, 0x0001);		// Display Control 1
	delay_nops(50);
	Mcupanel_RegSet(0x07, 0x0021);		// Display Control 1
	Mcupanel_RegSet(0x07, 0x0023);		// Display Control 1
	delay_nops(50);
	Mcupanel_RegSet(0x07, 0x0173);		// Display Control 1-----262K color and display ON
#endif

//############################MFC-S07001 V04##########################################
#if	(LCM_9320 == 9)

	delay_nops(10);
	//************* Start Initial Sequence **********//
	Mcupanel_RegSet(0x00, 0x0001);		// Start internal OSC.
	delay_nops(100);	
	Mcupanel_RegSet(0x01, 0x0000); //0x0100);		// set SS and SM bit
	Mcupanel_RegSet(0x02, 0x0400);		// set 1 line inversion
	Mcupanel_RegSet(0x03, 0x10b8); //0x1038); //0x1028); //0x1038);		// set GRAM write direction and BGR=1.
	Mcupanel_RegSet(0x04, 0x0000);		// Resize register
	Mcupanel_RegSet(0x08, 0x0202);		// set the back porch and front porch
	Mcupanel_RegSet(0x09, 0x0000);		// set non-display area refresh cycle ISC[3:0]
	Mcupanel_RegSet(0x0A, 0x0000);		// FMARK function
	Mcupanel_RegSet(0x0C, 0x0000);		// RGB interface setting
	Mcupanel_RegSet(0x0D, 0x0000);		// Frame marker Position
	Mcupanel_RegSet(0x0F, 0x0000);		// RGB interface polarity

	//*************Power On sequence ****************//    WCOM(0x51, 0x00, 0xEF);
	Mcupanel_RegSet(0x10, 0x0000);                // SAP, BT[3:0], AP, DSTB, SLP, STB
	Mcupanel_RegSet(0x11, 0x0007);                // DC1[2:0], DC0[2:0], VC[2:0]
	Mcupanel_RegSet(0x12, 0x0000);                // VREG1OUT voltage
	Mcupanel_RegSet(0x13, 0x0000);                // VDV[4:0] for VCOM amplitude
	delay_nops(50);

	Mcupanel_RegSet(0x10, 0x17B0);                // SAP, BT[3:0], AP, DSTB, SLP, STB
	Mcupanel_RegSet(0x11, 0x0001);                // DC1[2:0], DC0[2:0], VC[2:0]
	delay_nops(50);
	Mcupanel_RegSet(0x12, 0x013C); //0x0130);                // VREG1OUT voltage
	delay_nops(50);
	Mcupanel_RegSet(0x13, 0x1000); //0x1800);                // VDV[4:0] for VCOM amplitude
	Mcupanel_RegSet(0x29, 0x000d);//0x0004); //0x0005);                // VCM[4:0] for VCOMH
	delay_nops(50);
	Mcupanel_RegSet(0x20, 0x0000);                // GRAM horizontal Address
	Mcupanel_RegSet(0x21, 0x0000);                // GRAM Vertical Address
	Mcupanel_RegSet(0x2B, 0x0020);		// Frame Rate and Color Control-----16M_EN, Dither, FR_SEL[1:0]

	// ---------- Gamma Control  ---------- //
  	Mcupanel_RegSet(0x30, 0x0000);
  	Mcupanel_RegSet(0x31, 0x0306);
  	Mcupanel_RegSet(0x32, 0x0200);
  	Mcupanel_RegSet(0x35, 0x0107);
  	Mcupanel_RegSet(0x36, 0x0404);
  	Mcupanel_RegSet(0x37, 0x0606);
  	Mcupanel_RegSet(0x38, 0x0105);
  	Mcupanel_RegSet(0x39, 0x0707);
  	Mcupanel_RegSet(0x3C, 0x0600);
  	Mcupanel_RegSet(0x3D, 0x0807);
	// ---------- Window Address Area  ---------- //
	Mcupanel_RegSet(0x50, 0x0000);		// Horizontal GRAM Start Address-----HSA[7:0]
	Mcupanel_RegSet(0x51, 0x00EF);		// Horizontal GRAM End Address-----HEA[7:0]
	Mcupanel_RegSet(0x52, 0x0000);		// Vertical GRAM Start Address-----VSA[8:0]
	Mcupanel_RegSet(0x53, 0x013F);		// Vertical GRAM Start Address-----VEA[8:0]

	// ---------- Gate Scan Control  ---------- //
	Mcupanel_RegSet(0x60, 0x2700);		// GS, NL[5:0], SCN[5:0]
	Mcupanel_RegSet(0x61, 0x0001);		// NDL,VLE, REV
	Mcupanel_RegSet(0x6A, 0x0000);		// VL[8:0]

	// ---------- Partial Display Control  ---------- //
	Mcupanel_RegSet(0x80, 0x0000);		// Partial Image 1 Display Position-----PTDP0[8:0]
	Mcupanel_RegSet(0x81, 0x0000);		// Partial Image 1 Start Address-----PTSA0[8:0]
	Mcupanel_RegSet(0x82, 0x0000);		// Partial Image 1 End Address-----PTEA0[8:0]
	Mcupanel_RegSet(0x83, 0x0000);		// Partial Image 2 Display Position-----PTDP1[8:0]
	Mcupanel_RegSet(0x84, 0x0000);		// Partial Image 2 Start Address-----PTSA1[8:0]
	Mcupanel_RegSet(0x85, 0x0000);		// Partial Image 2 Start Address-----PTEA1[8:0]

	// ---------- Panel Interface Control  ---------- //
	Mcupanel_RegSet(0x90, 0x0013);		// Panel Interface Control 1-----DIVI[1:0], RTNI[4:0]
	Mcupanel_RegSet(0x92, 0x0000);		// Panel Interface Control 2-----NOWI[2:0]
	Mcupanel_RegSet(0x93, 0x0003);		// Panel Interface Control 3-----MCPI[2:0]
	Mcupanel_RegSet(0x95, 0x0110);		// Panel Interface Control 4-----DIVE[1:0], RTNE[5:0]
	Mcupanel_RegSet(0x97, 0x0000);		// Panel Interface Control 5-----NOWE[3:0]
	Mcupanel_RegSet(0x98, 0x0000);		// Panel Interface Control 6-----MCPE[2:0]

	Mcupanel_RegSet(0x07, 0x0001);		// Display Control 1
	delay_nops(50);
	Mcupanel_RegSet(0x07, 0x0021);		// Display Control 1
	Mcupanel_RegSet(0x07, 0x0023);		// Display Control 1
	delay_nops(50);
	Mcupanel_RegSet(0x07, 0x0173);		// Display Control 1-----262K color and display ON
#endif

//############################MFC-S07001 V04##########################################
#if	(LCM_9320 == 10)

	delay_nops(200);
	Mcupanel_RegSet(0x00E5, 0x8000); 	 // Set the internal vcore voltage
	Mcupanel_RegSet(0x0000, 0x0001); 	 // Start internal OSC.
	delay_nops(40);
	Mcupanel_RegSet(0x0001, 0x0000);	 // set SS and SM bit
	Mcupanel_RegSet(0x0002, 0x0700);	 // set 1 line inversion
	Mcupanel_RegSet(0x0003, 0x1038);	 // set GRAM write direction and BGR=1.
	Mcupanel_RegSet(0x0004, 0x0000);	 // Resize register

	Mcupanel_RegSet(0x0008, 0x0202);	 // set the back porch and front porch
	Mcupanel_RegSet(0x0009, 0x0000);	 // set non-display area refresh cycle ISC[3:0]
	Mcupanel_RegSet(0x000A, 0x0000);	 // FMARK function
	Mcupanel_RegSet(0x000C, 0x0000);		 // RGB interface setting
	Mcupanel_RegSet(0x000D, 0x0000);	 // Frame marker Position
	Mcupanel_RegSet(0x000F, 0x0000);		 // RGB interface polarity
	Mcupanel_RegSet(0x002b, 0x0020);   //frame rate and color control(0x0000)

	//*************Power On sequence ****************
	Mcupanel_RegSet(0x0010, 0x0000);		 // SAP, BT[3:0], AP, DSTB, SLP, STB
	Mcupanel_RegSet(0x0011, 0x0004);		 // DC1[2:0], DC0[2:0], VC[2:0]
	Mcupanel_RegSet(0x0012, 0x0000);		 // VREG1OUT voltage
	Mcupanel_RegSet(0x0013, 0x0000);		 // VDV[4:0] for VCOM amplitude
	delay_nops(200);				// Dis-charge capacitor power voltage

	Mcupanel_RegSet(0x0010, 0x17B0);		 // SAP, BT[3:0], AP, DSTB, SLP, STB
	Mcupanel_RegSet(0x0011, 0x0001);		 // DC1[2:0], DC0[2:0], VC[2:0]
	delay_nops(50);					 // Delay 50ms
	Mcupanel_RegSet(0x0012, 0x013e);		 // VREG1OUT voltage
	delay_nops(50);					 // Delay 50ms
	Mcupanel_RegSet(0x0013, 0x1c00);		 // VDV[4:0] for VCOM amplitude
	Mcupanel_RegSet(0x0029, 0x001e);		 // VCM[4:0] for VCOMH
	delay_nops(50);

	Mcupanel_RegSet(0x0020, 0x0000);		 // GRAM horizontal Address
	Mcupanel_RegSet(0x0021, 0x0000);		 // GRAM Vertical Address

	// ----------- Adjust the Gamma	Curve ----------//
	Mcupanel_RegSet(0x0030, 0x0002);
	Mcupanel_RegSet(0x0031, 0x0606);
	Mcupanel_RegSet(0x0032, 0x0501);


	Mcupanel_RegSet(0x0035, 0x0206);
	Mcupanel_RegSet(0x0036, 0x0504);
	Mcupanel_RegSet(0x0037, 0x0707);
	Mcupanel_RegSet(0x0038, 0x0306);
	Mcupanel_RegSet(0x0039, 0x0007);

	Mcupanel_RegSet(0x003C, 0x0700);
	Mcupanel_RegSet(0x003D, 0x0700);

	//------------------ Set GRAM area ---------------//
	Mcupanel_RegSet(0x0050, 0x0000);		// Horizontal GRAM Start Address
	Mcupanel_RegSet(0x0051, 0x00EF);		// Horizontal GRAM End Address
	Mcupanel_RegSet(0x0052, 0x0000);		// Vertical GRAM Start Address
	Mcupanel_RegSet(0x0053, 0x013F);		// Vertical GRAM Start Address


	Mcupanel_RegSet(0x0060, 0x2700);		// Gate Scan Line
	Mcupanel_RegSet(0x0061, 0x0001);		// NDL,VLE, REV
	Mcupanel_RegSet(0x006A, 0x0000);		// set scrolling line

	//-------------- Partial Display Control ---------//
	Mcupanel_RegSet(0x0080, 0x0000);
	Mcupanel_RegSet(0x0081, 0x0000);
	Mcupanel_RegSet(0x0082, 0x0000);
	Mcupanel_RegSet(0x0083, 0x0000);
	Mcupanel_RegSet(0x0084, 0x0000);
	Mcupanel_RegSet(0x0085, 0x0000);

	//-------------- Panel Control -------------------//