📄 hw_ili9320.c
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/******************************************************************/
/* Copyright (C) 2007 ROCK-CHIPS FUZHOU . All Rights Reserved. */
/*******************************************************************
File : hw_Ili9320.c
Desc : Mcupanel型号的Mcu驱动
Author : nzy
Date :
Notes :
$Log :
*********************************************************************/
#include "hw_include.h"
#if(LCDPANEL == MCUIF_ILI9320)
//#define LCM_9320 19
//1-->FPC-FST240W01天启;XDL T024001A0兴得利;KGM280I01-1A(NOPA);
//2-->9320日立玻璃HT3-LW; TT-1869; FPC-0047A
//3-->KGM280I01-1A(529D3&H3);
//4-->MFC-S07001 V04(奇美);;LT0728-FPC;;ST024001AO永佳;;T-0038A
//5-->KGM529D01-1A(9320琳达2.8)第一种;FPC-FTM280W03S天启
//6-->KGM529D01-1A(9320琳达2.8)第二种
//7-->ILI9320-CPT胜华2.8; XD028-V01
//8-->FPC-FTM280W03S天启
//9-->T-0022-B华瑞
//10-->ST024001AO第二种 永佳
//11-->FPC090012-1 V01 永佳
//12-->FPC-FTS240F01(飞尔)
//13-->FPC-FTS240F15(1505驱动)
//14-->AST24008C05-V1(9325驱动)
//15-->FPC28T23-B(ALH2.8),AF283E1-37A V1.2(ALH2.8)3.3V
//16-->JLST028005AO v1.0(9325 2.8)
//17-->CF24LGG31-36AV1
//18-->T-0038A
//19-->发掘9320
//20-->T-0012-B(9325 2.4)
//21-->XT280364SK(9325 2.8祥龙)
//22-->AF283E1-37A V1.2(ALH2.8)3.0V
//23-->KIC2802IH37M-FPC(小叶2.8)3.0V
//24-->XT280374PK(9325 2.8祥龙)
//#if ((LCM_9320 == 14)|(LCM_9320 == 16))
// #define LCM_9325
//#endif
/*---------------------------------------------------------
Name : Mcupanel_PowerOnInit
Desc : Mcupanel上电初始化
Params:
Return:
Author: nzy
Date :
-----------------------------------------------------------*/
void Mcupanel_PowerOnInit(void)
{
UINT32 i,j;
Lcdctrl_McuBypassMode(TRUE);
//############################FPC-FST240W01天启;XDL T024001A0兴得利##########################################
#if (LCM_9320 == 1)
delay_nops(200);
Mcupanel_RegSet(0x00E5, 0x8000); // Set the internal vcore voltage
Mcupanel_RegSet(0x0000, 0x0001); // Start internal OSC.
delay_nops(40);
Mcupanel_RegSet(0x0001, 0x0000); // set SS and SM bit
Mcupanel_RegSet(0x0002, 0x0700); // set 1 line inversion
Mcupanel_RegSet(0x0003, 0x1038); // set GRAM write direction and BGR=1.
Mcupanel_RegSet(0x0004, 0x0000); // Resize register
Mcupanel_RegSet(0x0008, 0x0202); // set the back porch and front porch
Mcupanel_RegSet(0x0009, 0x0000); // set non-display area refresh cycle ISC[3:0]
Mcupanel_RegSet(0x000A, 0x0000); // FMARK function
Mcupanel_RegSet(0x000C, 0x0000); // RGB interface setting
Mcupanel_RegSet(0x000D, 0x0000); // Frame marker Position
Mcupanel_RegSet(0x000F, 0x0000); // RGB interface polarity
Mcupanel_RegSet(0x002b, 0x0020); //frame rate and color control(0x0000)
//*************Power On sequence ****************
Mcupanel_RegSet(0x0010, 0x0000); // SAP, BT[3:0], AP, DSTB, SLP, STB
Mcupanel_RegSet(0x0011, 0x0007); // DC1[2:0], DC0[2:0], VC[2:0]
Mcupanel_RegSet(0x0012, 0x0000); // VREG1OUT voltage
Mcupanel_RegSet(0x0013, 0x0000); // VDV[4:0] for VCOM amplitude
delay_nops(200); // Dis-charge capacitor power voltage
Mcupanel_RegSet(0x0010, 0x17B0); // SAP, BT[3:0], AP, DSTB, SLP, STB
Mcupanel_RegSet(0x0011, 0x0004); // DC1[2:0], DC0[2:0], VC[2:0]
delay_nops(50); // Delay 50ms
Mcupanel_RegSet(0x0012, 0x013c); // VREG1OUT voltage
delay_nops(50); // Delay 50ms
Mcupanel_RegSet(0x0013, 0x1700); // VDV[4:0] for VCOM amplitude
Mcupanel_RegSet(0x0029, 0x0015); // VCM[4:0] for VCOMH
delay_nops(50);
Mcupanel_RegSet(0x0020, 0x0000); // GRAM horizontal Address
Mcupanel_RegSet(0x0021, 0x0000); // GRAM Vertical Address
// ----------- Adjust the Gamma Curve ----------//
Mcupanel_RegSet(0x0030, 0x0002);
Mcupanel_RegSet(0x0031, 0x0606);
Mcupanel_RegSet(0x0032, 0x0501);
Mcupanel_RegSet(0x0035, 0x0206);
Mcupanel_RegSet(0x0036, 0x0504);
Mcupanel_RegSet(0x0037, 0x0707);
Mcupanel_RegSet(0x0038, 0x0306);
Mcupanel_RegSet(0x0039, 0x0007);
Mcupanel_RegSet(0x003C, 0x0700);
Mcupanel_RegSet(0x003D, 0x0700);
//------------------ Set GRAM area ---------------//
Mcupanel_RegSet(0x0050, 0x0000); // Horizontal GRAM Start Address
Mcupanel_RegSet(0x0051, 0x00EF); // Horizontal GRAM End Address
Mcupanel_RegSet(0x0052, 0x0000); // Vertical GRAM Start Address
Mcupanel_RegSet(0x0053, 0x013F); // Vertical GRAM Start Address
Mcupanel_RegSet(0x0060, 0x2700); // Gate Scan Line
Mcupanel_RegSet(0x0061, 0x0001); // NDL,VLE, REV
Mcupanel_RegSet(0x006A, 0x0000); // set scrolling line
//-------------- Partial Display Control ---------//
Mcupanel_RegSet(0x0080, 0x0000);
Mcupanel_RegSet(0x0081, 0x0000);
Mcupanel_RegSet(0x0082, 0x0000);
Mcupanel_RegSet(0x0083, 0x0000);
Mcupanel_RegSet(0x0084, 0x0000);
Mcupanel_RegSet(0x0085, 0x0000);
//-------------- Panel Control -------------------//
Mcupanel_RegSet(0x0090, 0x0010);
Mcupanel_RegSet(0x0092, 0x0000);
Mcupanel_RegSet(0x0093, 0x0003);
Mcupanel_RegSet(0x0095, 0x0110);
Mcupanel_RegSet(0x0097, 0x0000);
Mcupanel_RegSet(0x0098, 0x0000);
Mcupanel_RegSet(0x0007, 0x0173); // 262K color and display ON
Mcupanel_Command(0x0022);
#endif
//############################HT-LW##########################################
#if (LCM_9320 == 2)
Mcupanel_RegSet(0x0000,0x0001); //start osc
delay_nops(20);
Mcupanel_RegSet(0x0001,0x0000); //driver output control
Mcupanel_RegSet(0x0002,0x0400); //driving wave control
Mcupanel_RegSet(0x0003,0x1038); //entyr mode set(0x1030)
Mcupanel_RegSet(0x0004,0x0000); //resizing register
Mcupanel_RegSet(0x0007,0x0000); //display control1
Mcupanel_RegSet(0x0008,0x0202); //display control2
Mcupanel_RegSet(0x0009,0x0100); //siplay control3 (0x0000)
Mcupanel_RegSet(0x000a,0x0008); //display control4 (0x000f),(0x0008)
Mcupanel_RegSet(0x000c,0x0000); // rgb interface input control1(0x0003)
Mcupanel_RegSet(0x000b,0x0000);
Mcupanel_RegSet(0x000d,0x0000); //frame marker position
Mcupanel_RegSet(0x002b,0x0010); //frame rate and color control(0x0000)
Mcupanel_RegSet(0x0097,0x0000); //pannel interface control1
Mcupanel_RegSet(0x000f,0x0000); //rgb interface input control2
Mcupanel_RegSet(0x0010,0x0000); //power control1(0x1ff0)(0x0000)
delay_nops(20);
Mcupanel_RegSet(0x0011,0x0000); //power control2
Mcupanel_RegSet(0x0012,0x0000); // power control3
delay_nops(60);
Mcupanel_RegSet(0x0013,0x1000); //power control4 (0x0000)
delay_nops(60);
/****************************power control end ************************/
Mcupanel_RegSet(0x0056,0x080F);
Mcupanel_RegSet(0x0010,0x17b0); //(0x1ff0)
delay_nops(20);
Mcupanel_RegSet(0x0011,0x0004); //(0x0000)
Mcupanel_RegSet(0x0012,0x013A); //(0x0118)
delay_nops(60);
Mcupanel_RegSet(0x13, 0x0500); //0000); // VDV[4:0] for VCOM amplitude
Mcupanel_RegSet(0x29, 0x0005); //B);
delay_nops(50);
// ---------- Gamma Control ---------- //
Mcupanel_RegSet(0x30, 0x0102);
Mcupanel_RegSet(0x31, 0x0C1B);
Mcupanel_RegSet(0x32, 0x121F);
Mcupanel_RegSet(0x33, 0x391A);
Mcupanel_RegSet(0x34, 0x380B);
Mcupanel_RegSet(0x35, 0x1004);
Mcupanel_RegSet(0x36, 0x1701);
Mcupanel_RegSet(0x37, 0x0A1E);
Mcupanel_RegSet(0x38, 0x0007);
Mcupanel_RegSet(0x39, 0x0101);
Mcupanel_RegSet(0x3A, 0x0C06);
Mcupanel_RegSet(0x3B, 0x0F03);
Mcupanel_RegSet(0x3C, 0x000C);
Mcupanel_RegSet(0x3D, 0x0D0C);
Mcupanel_RegSet(0x3E, 0x0504);
Mcupanel_RegSet(0x3F, 0x0601);
Mcupanel_RegSet(0x0020,0x0000);
Mcupanel_RegSet(0x0021,0x0000);
Mcupanel_RegSet(0x0060,0x2700);
Mcupanel_RegSet(0x0061,0x0001);
Mcupanel_RegSet(0x006a,0x0000);
Mcupanel_RegSet(0x0050,0x0000);
Mcupanel_RegSet(0x0051,0x00f0);
Mcupanel_RegSet(0x0052,0x0000);
Mcupanel_RegSet(0x0053,0x0140);
//Mcupanel_RegSet(0x0045,0xdb00);
/*************gate scan control ***********************/
Mcupanel_RegSet(0x0007,0x0005); //00,05
delay_nops(60);
Mcupanel_RegSet(0x0007,0x0025); //(0x0025)
delay_nops(60);
Mcupanel_RegSet(0x0007,0x0027); //00,27
delay_nops(60);
Mcupanel_RegSet(0x0007,0x0137);
delay_nops(60);
Mcupanel_Command(0x0022);
#endif
//############################KGM280I--LINDA9320##########################################
#if (LCM_9320 == 3)
delay_nops(10);
//-------------------------------
//************* Start Initial Sequence **********//
Mcupanel_RegSet(0x00, 0x0000); //0001); // Start internal OSC.
Mcupanel_RegSet(0x01, 0x0000); //0x0100); // set SS and SM bit
Mcupanel_RegSet(0x02, 0x0700); //0400); // set 1 line inversion
Mcupanel_RegSet(0x03, 0x10b8); //0x1038); //0x1028); //0x1038); // set GRAM write direction and BGR=1.
Mcupanel_RegSet(0x04, 0x0000); // Resize register
Mcupanel_RegSet(0x08, 0x0207); //0202); // set the back porch and front porch
Mcupanel_RegSet(0x09, 0x0000); // set non-display area refresh cycle ISC[3:0]
Mcupanel_RegSet(0x0A, 0x0000); // FMARK function
Mcupanel_RegSet(0x0C, 0x0000); // RGB interface setting
Mcupanel_RegSet(0x0D, 0x0000); // Frame marker Position
Mcupanel_RegSet(0x0F, 0x0000); // RGB interface polarity
//*************Power On sequence ****************// WCOM(0x51, 0x00, 0xEF);
Mcupanel_RegSet(0x07, 0x0101);
Mcupanel_RegSet(0x10, 0x10B0); //0000); // SAP, BT[3:0], AP, DSTB, SLP, STB
Mcupanel_RegSet(0x11, 0x0007); // DC1[2:0], DC0[2:0], VC[2:0]
delay_nops(50);
Mcupanel_RegSet(0x07, 0x0001);
Mcupanel_RegSet(0x12, 0x0138); //0000); // VREG1OUT voltage
delay_nops(50);
Mcupanel_RegSet(0x13, 0x0500); //0000); // VDV[4:0] for VCOM amplitude
Mcupanel_RegSet(0x29, 0x0009); //B);
delay_nops(50);
// ---------- Gamma Control ---------- //
Mcupanel_RegSet(0x30, 0x0102);
Mcupanel_RegSet(0x31, 0x0C1B);
Mcupanel_RegSet(0x32, 0x121F);
Mcupanel_RegSet(0x33, 0x391A);
Mcupanel_RegSet(0x34, 0x380B);
Mcupanel_RegSet(0x35, 0x1004);
Mcupanel_RegSet(0x36, 0x1701);
Mcupanel_RegSet(0x37, 0x0A1E);
Mcupanel_RegSet(0x38, 0x0007);
Mcupanel_RegSet(0x39, 0x0101);
Mcupanel_RegSet(0x3A, 0x0C06);
Mcupanel_RegSet(0x3B, 0x0F03);
Mcupanel_RegSet(0x3C, 0x000C);
Mcupanel_RegSet(0x3D, 0x0D0C);
Mcupanel_RegSet(0x3E, 0x0504);
Mcupanel_RegSet(0x3F, 0x0601);
// ---------- Window Address Area ---------- //
Mcupanel_RegSet(0x50, 0x0000); // Horizontal GRAM Start Address-----HSA[7:0]
Mcupanel_RegSet(0x51, 0x00EF); // Horizontal GRAM End Address-----HEA[7:0]
Mcupanel_RegSet(0x52, 0x0000); // Vertical GRAM Start Address-----VSA[8:0]
Mcupanel_RegSet(0x53, 0x013F); // Vertical GRAM Start Address-----VEA[8:0]
// ---------- Gate Scan Control ---------- //
Mcupanel_RegSet(0x60, 0x2700); // GS, NL[5:0], SCN[5:0]
Mcupanel_RegSet(0x61, 0x0001); // NDL,VLE, REV
Mcupanel_RegSet(0x6A, 0x0000); // VL[8:0]
// ---------- Partial Display Control ---------- //
Mcupanel_RegSet(0x80, 0x0000); // Partial Image 1 Display Position-----PTDP0[8:0]
Mcupanel_RegSet(0x81, 0x0000); // Partial Image 1 Start Address-----PTSA0[8:0]
Mcupanel_RegSet(0x82, 0x0000); // Partial Image 1 End Address-----PTEA0[8:0]
Mcupanel_RegSet(0x83, 0x0000); // Partial Image 2 Display Position-----PTDP1[8:0]
Mcupanel_RegSet(0x84, 0x0000); // Partial Image 2 Start Address-----PTSA1[8:0]
Mcupanel_RegSet(0x85, 0x0000); // Partial Image 2 Start Address-----PTEA1[8:0]
// ---------- Panel Interface Control ---------- //
Mcupanel_RegSet(0x90, 0x0013); // Panel Interface Control 1-----DIVI[1:0], RTNI[4:0]
Mcupanel_RegSet(0x92, 0x0000); // Panel Interface Control 2-----NOWI[2:0]
Mcupanel_RegSet(0x93, 0x0103); // Panel Interface Control 3-----MCPI[2:0]
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