hwinit.s

Windows CE 6.0 BSP for the Beagle Board.

		; write a specific sequence to manual command 
		; register before configuring MRC register - CS0/1.
		ldr     r1, =BSP_SDRC_MANUAL_NOP_CMD 		  ; NOP comand
		str     r1, [r0,#OMAP2420_SDRC_MANUAL_0_OA]	
		str     r1, [r0,#OMAP2420_SDRC_MANUAL_1_OA]	
		
		ldr     r1, =BSP_SDRC_MANUAL_PRECHARGE_CMD	  ; Precharge
		str     r1, [r0,#OMAP2420_SDRC_MANUAL_0_OA]
		str     r1, [r0,#OMAP2420_SDRC_MANUAL_1_OA]
		
		ldr     r1, =BSP_SDRC_MANUAL_AUTOREFRESH_CMD ; Auto-refresh command.
		str     r1, [r0,#OMAP2420_SDRC_MANUAL_0_OA]
		str     r1, [r0]                                  ; Auto-refresh command again.
		str     r1, [r0,#OMAP2420_SDRC_MANUAL_1_OA]
		str     r1, [r0]                                  ; Auto-refresh command again.
						                    
		; configure mr register for CS0/1
		ldr     r1, =BSP_SDRC_MR_VAL
		str     r1, [r0,#OMAP2420_SDRC_MR_0_OA]
		str     r1, [r0,#OMAP2420_SDRC_MR_1_OA]
		
		ldr     r1, =BSP_SDRC_DLL_VAL1	               
		str     r1, [r0,#OMAP2420_SDRC_DLLA_CTRL_OA]
		str     r1, [r0,#OMAP2420_SDRC_DLLB_CTRL_OA]
		
		ldr     r1, =BSP_SDRC_DLL_VAL2		        
		str     r1, [r0,#OMAP2420_SDRC_DLLA_CTRL_OA]
		str     r1, [r0,#OMAP2420_SDRC_DLLB_CTRL_OA]
		
		nop
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		nop
		nop
		nop
		nop
		nop
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		nop
		
	   ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
	   ; CONFIGURE GPMC for CS0
	   ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		
       ldr   r0, =OMAP2420_GPMC_REGS_PA

       ldr   r1, =BSP_GPMC_TIMEOUT_CONTROL_VAL
       str   r1, [r0,#OMAP2420_GPMC_TIMEOUT_CONTROL_OA]

       ldr   r1, =BSP_GPMC_SYSCONFIG_VAL
       str	 r1, [r0,#OMAP2420_GPMC_SYSCONFIG_OA]


       ldr   r1, =BSP_GPMC_IRQENABLE_VAL 
       str	 r1, [r0,#OMAP2420_GPMC_IRQENABLE_OA]

       ldr   r1, =BSP_GPMC_CONFIG_VAL 
       str	 r1, [r0,#OMAP2420_GPMC_CONFIG_OA]
       ; Make sure CS0 is not pointing to the same place.

       ;****Warning****
	   ;The config value to CONFIG7 register is valid only for
	   ;NAND flash. If hwinit.s is used for NOR then we should not 
	   ;configure CONFIG7 register.
  
       ldr   r1, =BSP_GPMC_CONFIG1_0_VAL   
       str	 r1, [r0,#OMAP2420_GPMC_CONFIG1_0_OA]

       ldr   r1, =BSP_GPMC_CONFIG2_0_VAL   
       str	 r1, [r0,#OMAP2420_GPMC_CONFIG2_0_OA]

       ldr   r1, =BSP_GPMC_CONFIG3_0_VAL   
       str	 r1, [r0,#OMAP2420_GPMC_CONFIG3_0_OA]

       ldr   r1, =BSP_GPMC_CONFIG4_0_VAL   
       str	 r1, [r0,#OMAP2420_GPMC_CONFIG4_0_OA]

       ldr   r1, =BSP_GPMC_CONFIG5_0_VAL   
       str	 r1, [r0,#OMAP2420_GPMC_CONFIG5_0_OA]

       ldr   r1, =BSP_GPMC_CONFIG6_0_VAL   
       str	 r1, [r0,#OMAP2420_GPMC_CONFIG6_0_OA]

       ldr   r1, =BSP_GPMC_CONFIG7_0_VAL   
       str	 r1, [r0,#OMAP2420_GPMC_CONFIG7_0_OA]

       ;-------------------------------------------------------------------
	   ; GPMC settings for MPDB CS1
	   ;-------------------------------------------------------------------

       ldr   r1, =BSP_GPMC_CONFIG1_1_VAL
       str   r1, [r0,#OMAP2420_GPMC_CONFIG1_1_OA]
			
       ldr   r1, =BSP_GPMC_CONFIG2_1_VAL
       str   r1, [r0,#OMAP2420_GPMC_CONFIG2_1_OA]
		
       ldr   r1, =BSP_GPMC_CONFIG3_1_VAL
       str   r1, [r0,#OMAP2420_GPMC_CONFIG3_1_OA]

       ldr   r1, =BSP_GPMC_CONFIG4_1_VAL  
       str   r1, [r0,#OMAP2420_GPMC_CONFIG4_1_OA]

       ldr   r1, =BSP_GPMC_CONFIG5_1_VAL
       str   r1, [r0,#OMAP2420_GPMC_CONFIG5_1_OA]
		
       ldr   r1, =BSP_GPMC_CONFIG6_1_VAL
       str   r1, [r0,#OMAP2420_GPMC_CONFIG6_1_OA]
				
       ldr   r1, =BSP_GPMC_CONFIG7_1_VAL	
       str   r1, [r0,#OMAP2420_GPMC_CONFIG7_1_OA]
         
	   ;SDRC and GPMC configuration ends here


        ; Clean & invalidate D cache
;110
;		mrc     p15, 0, r15, c7, c14, 3
;        bne     %b110
        
        ; Invalidate I cache
        mov     r0, #0
        mcr     p15, 0, r0, c7, c5, 0
       
        ; Disable I and D caches and write buffer
        mrc     p15, 0, r0, c1, c0, 0
        ldr		r1, =0xFFFFEFF3	        
        and     r0, r0, r1           ; I-cache, D-cache, write buffer
        mcr     p15, 0, r0, c1, c0, 0

;11		ldr   r0, =0x08000016
		ldr   r0, =0x08000016
        ldr   r1, =0xFF00 ;LED_REG_VAL1
        strh  r1, [r0]
;	    b	%b11

       ;*-------------------------------------------
	   ; Configure PRCM registers
	   ;*-------------------------------------------

	   ; Configure the Core clock source to be DPLL, by default it is DPLL * 2.
	   ; Set Core clock = DPLL
	   ldr r0, =OMAP2420_PRCM_REGS_PA
	   ; Allow the core clk to use the default value of DPLL * 2.
  
       ldr r1, [r0,#OMAP2420_PRCM_CM_CLKSEL2_PLL_OA]
       bic r1, r1,#BSP_PRCM_CM_CLKSEL2_PLL_MASK     ; Clear bits 0,1
       orr r1, r1,#BSP_PRCM_CM_CLKSEL2_PLL_DPLL_SET ; core = dpll * 1
       str r1,[r0,#OMAP2420_PRCM_CM_CLKSEL2_PLL_OA]
                
	   ;Put DPLL in low power bypass.
       ;Configure the value for CM_CLKEN_PLL[1:0] (EN_DPLL)
       ldr r1,[r0,#OMAP2420_PRCM_CM_CLKEN_PLL_OA]
       bic r1,r1,#BSP_PRCM_CM_CLKEN_PLL_MASK1
       orr r1,r1,#BSP_PRCM_CM_CLKEN_PLL_DPLL_SET1
       str r1,[r0,#OMAP2420_PRCM_CM_CLKEN_PLL_OA]
        
       ;Select MPU clock
       ;configure the value for CM_CLKSEL_MPU[4:0]
       ldr r1,[r0,#OMAP2420_PRCM_CM_CLKSEL_MPU_OA]
       bic r1,r1,#BSP_PRCM_CM_CLKSEL_MPU_MASK
       orr r1,r1,#BSP_PRCM_CM_CLKSEL_MPU_SET      ; mpu clock = core clock / 2
       str r1,[r0,#OMAP2420_PRCM_CM_CLKSEL_MPU_OA]
        
       ;Select DSP clock
       ;configure the value for CM_CLKSEL_DSP[13:0]
       ldr r1, =BSP_PRCM_CM_CLKSEL_DSP_VAL	
       str r1,[r0,#OMAP2420_PRCM_CM_CLKSEL_DSP_OA]	
        
       ;Select GFX clock
       ;configure the value for CM_CLKSEL_GFX[2:0]
       ldr r1, =BSP_PRCM_CM_CLKSEL_GFX_VAL	
       str r1,[r0,#OMAP2420_PRCM_CM_CLKSEL_GFX_OA]
        
       ;Select 
       ;configure the value for CM_CLKSEL1_CORE
       ldr r1, =BSP_PRCM_CM_CLKSEL1_CORE_VAL
       str r1,[r0,#OMAP2420_PRCM_CM_CLKSEL1_CORE_OA]
        
	   ;Now check for clock validity and make all the PRCM changes effective.
       ldr r1,[r0,#OMAP2420_PRCM_CLKCFG_STATUS_OA]	
       and r1, r1, #0x01 	; Check if bit 0 is ONE.
       cmp r1,#0x01	
       bne %F50          	; If it is 1 then stay in a forever loop,
                            ; otherwise proceed to prcm_validate.
40      nop
       b %B40     			; stay in a forever loop.         
         
50
       mov r1,#0x01		    ; write 1 into bit 0 of PRCM_CLKCFG_CTRL register
       str r1,[r0,#OMAP2420_PRCM_CLKCFG_CTRL_OA]
		
       ; Start configuring the Level 0 registers
       ; DPLL is 300
	   ; Selects 12MHz for the APLL
       ldr r1, =BSP_PRCM_CM_CLKSEL1_PLL_VAL 
       str r1,[r0,#OMAP2420_PRCM_CM_CLKSEL1_PLL_OA]
       
       ;Enable APLL 96MHz.
       ;Retain the default value for CM_CLKEN_PLL register EN_96_PLL
       ;Retain the default value for CM_AUTOIDLE_PLL[3:2] (AUTO_96M)
        
       ;Enable APLL 54MHz.
       ;Configure the value for CM_CLKEN_PLL[7:6] (EN_54M_PLL)
       ldr r1,[r0,#OMAP2420_PRCM_CM_CLKEN_PLL_OA]
       bic r1,r1,#BSP_PRCM_CM_CLKEN_PLL_MASK2
       orr r1,r1,#BSP_PRCM_CM_CLKEN_PLL_APLL_SET
       str r1,[r0,#OMAP2420_PRCM_CM_CLKEN_PLL_OA]

       ;Retain the default value for CM_AUTOIDLE_PLL[7:6] (AUTO_54M)
	   ;Scale up the processor speed.
       ;Configure CM_CLKSEL1_PLL[21:12] - multiplication factor
       ;CM_CLKSEL1_PLL[11:8] - division factor
 	   
       ;Configure the value for CM_CLKEN_PLL[1:0] (EN_DPLL)
       bic r1,r1,#BSP_PRCM_CM_CLKEN_PLL_MASK1
       orr r1,r1,#BSP_PRCM_CM_CLKEN_PLL_DPLL_SET2
        
       ;* loop for 4000 times *;
       mov r6, #0xFF0  ; load 1024 in r0
60
       nop
       subs r6, r6, #1 ; decrement by one
       cmp r6, #0x0    ; check if its equal to 0
	   bne %B60
		str r1,[r0,#OMAP2420_PRCM_CM_CLKEN_PLL_OA]
        
       mov r6, #0xFF0  ; load 1024 in r0
70
       nop
       subs r6, r6, #1 ; decrement by one
       cmp r6, #0x0    ; check if its equal to 0
       bne %B70
        
       nop
       nop
       nop
       nop
                
       ;Configuration of Level 0 registers ends here.
        
       ;Start configuring the Level 1 registers.
       ;Retain the Default value of CM_CLKSEL1_PLL1[3] (48M_source)
       ;and CM_CLKSEL1_PLL1[5] (54M_source) which means the source for these
       ;clocks is from 96 MHz APLL, 54 MHz APLL respectively. 
        
       ;Configure the MPU clock. CM_CLKSEL_MPU [4:0] is by default 1
       ;which means MPU_CLK = Core_clk/1. So it is 12 MHz.
        
       ;PRCM_CLKOUT_CTRL[1:0](ClkOut_source) must be made 1. 
       ;since the clock out is connected to Codec, which requires 12 MHz MCLK, 
       ;make the source as system clock which is 12MHz
       ldr r1,[r0, #OMAP2420_PRCM_CLKOUT_CTRL_OA] 
       bic r1,r1,#BSP_PRCM_CLKOUT_CTRL_MASK	;clear the bits 0,1
       orr r1,r1,#BSP_PRCM_CLKOUT_CTRL_SET	;enable bit number 0 for 12MHz sys clock out, 7 to enable sys clock out
       str r1,[r0, #OMAP2420_PRCM_CLKOUT_CTRL_OA] 
                
       ;Configuration of Level 1 registers ends here.
        	        	
       ;--------------------------------------------
	   ;         PRCM Modules Clock Enable
       ;--------------------------------------------
        
       ldr r0, =OMAP2420_PRCM_REGS_PA
       ldr r1, =BSP_PRCM_CLKEMUL_CTRL_VAL 
       str r1,[r0,#OMAP2420_PRCM_CLKEMUL_CTRL_OA]
       ldr r1, =BSP_PRCM_CM_xCLKENx_CORE_VAL
       str r1,[r0,#OMAP2420_PRCM_CM_FCLKEN1_CORE_OA] 
       str r1,[r0,#OMAP2420_PRCM_CM_FCLKEN2_CORE_OA]
       str r1,[r0,#OMAP2420_PRCM_CM_ICLKEN1_CORE_OA]
       str r1,[r0,#OMAP2420_PRCM_CM_ICLKEN2_CORE_OA]
       ldr r1, =BSP_PRCM_CM_CLKSEL2_CORE_VAL
       str r1,[r0,#OMAP2420_PRCM_CM_CLKSEL2_CORE_OA] ;set GPTn clk to sysclk (only one available)
       ldr r1, =BSP_PRCM_CM_CLKSEL_WKUP_VAL ;0x01 
       str r1,[r0,#OMAP2420_PRCM_CM_CLKSEL_WKUP_OA]  ;set GPT1 clk to sysclk (only one available)
       ldr r1, =BSP_PRCM_CM_FCLKEN_WKUP_VAL ;0x0F 
       str r1,[r0,#OMAP2420_PRCM_CM_FCLKEN_WKUP_OA]
       ldr r1, =BSP_PRCM_CM_ICLKEN_WKUP_VAL ;0x3F 
       str r1,[r0,#OMAP2420_PRCM_CM_ICLKEN_WKUP_OA]
    	
       nop
    	
       ;------Coprocessor Control reset-------
       ;--------------------------------------
       MOV r0, #0x00050000
       ADD r0, r0, #0x78
       MCR p15, 0, r0, c1, c0, 0 ; reset Control Coprocessor register
       ;--------------------------------------
	
	   ;--------Peripheral port mapping-------
	   ;--------------------------------------
       LDR r0,=0x480FE003                    ;INTH_SETUP (Need to check this register, Not available in 2420 TRM)
       MCR p15, 0, r0, c15, c2, 4

       LDR r3,=0x00008000                    ; L4 MASK
       MCR p15, 0, r3, c1, c0, 0
  	 
;-------------------------------------------------------------------------------

        END