omap3_base_regs.h

Windows CE 6.0 BSP for the Beagle Board.

//  32kHz Sync Timer
//------------------------------------------------------------------------------

#define OMAP3_TIMER32K_REGS_PA			(OMAP3_WAKEUP_L4_REGS_PA+0x00020000)

//------------------------------------------------------------------------------
//  General Purpose Timers
//------------------------------------------------------------------------------

#define OMAP3_GPTIMER1_REGS_PA			(OMAP3_WAKEUP_L4_REGS_PA+0x00018000)
#define OMAP3_GPTIMER2_REGS_PA			(OMAP3_PER_L4_REGS_PA+0x00032000)
#define OMAP3_GPTIMER3_REGS_PA			(OMAP3_PER_L4_REGS_PA+0x00034000)
#define OMAP3_GPTIMER4_REGS_PA			(OMAP3_PER_L4_REGS_PA+0x00036000)
#define OMAP3_GPTIMER5_REGS_PA			(OMAP3_PER_L4_REGS_PA+0x00038000)
#define OMAP3_GPTIMER6_REGS_PA			(OMAP3_PER_L4_REGS_PA+0x0003A000)
#define OMAP3_GPTIMER7_REGS_PA			(OMAP3_PER_L4_REGS_PA+0x0003C000)
#define OMAP3_GPTIMER8_REGS_PA			(OMAP3_PER_L4_REGS_PA+0x0003E000)
#define OMAP3_GPTIMER9_REGS_PA			(OMAP3_PER_L4_REGS_PA+0x00040000)
#define OMAP3_GPTIMER10_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x00086000)
#define OMAP3_GPTIMER11_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x00088000)
#define OMAP3_GPTIMER12_REGS_PA			(OMAP3_WAKEUP_L4_REGS_PA+0x00004000)

//------------------------------------------------------------------------------
//  Watchdog Timers
//------------------------------------------------------------------------------

#define OMAP3_WDOG1_REGS_PA				(OMAP3_WAKEUP_L4_REGS_PA+0x0000C000)
#define OMAP3_WDOG2_REGS_PA				(OMAP3_WAKEUP_L4_REGS_PA+0x00014000)
#define OMAP3_WDOG3_REGS_PA				(OMAP3_PER_L4_REGS_PA+0x00030000)

//------------------------------------------------------------------------------
//  Mailbox
//------------------------------------------------------------------------------

#define OMAP3_MAILBOX_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x00094000)

//------------------------------------------------------------------------------
//  MagicGate
//------------------------------------------------------------------------------

#define OMAP3_MG_REG_PA					(OMAP3_CORE_L4_REGS_PA+0x000B0000)

//------------------------------------------------------------------------------
//  MMC/SDIO Module
//------------------------------------------------------------------------------

#define OMAP3_MMCHS1_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x0009C000)
#define OMAP3_MMCHS2_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x000B4000)
#define OMAP3_MMCHS3_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x000AD000)

//------------------------------------------------------------------------------
//  Memory Stick PRO Module
//------------------------------------------------------------------------------

#define OMAP3_MSPRO_REGS_PA				(OMAP3_CORE_L4_REGS_PA+0x0009E000)

//------------------------------------------------------------------------------
//  HDQ/1Wire Controller
//------------------------------------------------------------------------------

#define OMAP3_HDQ_1WIRE_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x000B2000)

//------------------------------------------------------------------------------
//  Camera Controller
//------------------------------------------------------------------------------

#define OMAP3_CAMISP_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x000BC000)
#define OMAP3_CAMISP_CBUFF_REGS_PA		(OMAP3_CORE_L4_REGS_PA+0x000BC100)
#define OMAP3_CAMISP_CCDC_REGS_PA		(OMAP3_CORE_L4_REGS_PA+0x000BC600)
#define OMAP3_CAMISP_HIST_REGS_PA		(OMAP3_CORE_L4_REGS_PA+0x000BCA00)
#define OMAP3_CAMISP_H3A_REGS_PA		(OMAP3_CORE_L4_REGS_PA+0x000BCC00)
#define OMAP3_CAMISP_PREVIEW_REGS_PA	(OMAP3_CORE_L4_REGS_PA+0x000BCE00)
#define OMAP3_CAMISP_RESIZER_REGS_PA	(OMAP3_CORE_L4_REGS_PA+0x000BD000)
#define OMAP3_CAMISP_SBL_REGS_PA		(OMAP3_CORE_L4_REGS_PA+0x000BD200)

//------------------------------------------------------------------------------
//  GPIO Controllers
//------------------------------------------------------------------------------

#define OMAP3_GPIO1_REGS_PA				(OMAP3_WAKEUP_L4_REGS_PA+0x00010000)
#define OMAP3_GPIO2_REGS_PA				(OMAP3_PER_L4_REGS_PA+0x00050000)
#define OMAP3_GPIO3_REGS_PA				(OMAP3_PER_L4_REGS_PA+0x00052000)
#define OMAP3_GPIO4_REGS_PA				(OMAP3_PER_L4_REGS_PA+0x00054000)
#define OMAP3_GPIO5_REGS_PA				(OMAP3_PER_L4_REGS_PA+0x00056000)
#define OMAP3_GPIO6_REGS_PA				(OMAP3_PER_L4_REGS_PA+0x00058000)

//------------------------------------------------------------------------------
//  Interrupt Controller
//------------------------------------------------------------------------------

#define OMAP3_INTC_MPU_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x00200000)

//------------------------------------------------------------------------------
//  USB Device Controller
//------------------------------------------------------------------------------

#define OMAP2420_USBD_REGS_PA           (0x4805E200)

//------------------------------------------------------------------------------
//  IVA MMU base address
//------------------------------------------------------------------------------

#define OMAP2420_IVA_MMU_REGS_PA        (0x5D000000)

//------------------------------------------------------------------------------
//  EAC Controller
//------------------------------------------------------------------------------

#define OMAP2420_EAC_REGS_PA            (0x48090000)

//------------------------------------------------------------------------------
//  DSP MMU Controller
//------------------------------------------------------------------------------

#define OMAP2420_DSP_MMU_REGS_PA        (0x5A000000)

//------------------------------------------------------------------------------
//  SRAM embedded memory
//------------------------------------------------------------------------------

#define OMAP2420_SRAM_SIZE              (640*1024)
#define OMAP2420_SRAM_PA                (0x40206000)

//-----------------------------------------------------------------------------
// SDRAM for Display
//-----------------------------------------------------------------------------

#define OMAP2420_SDRAM_LCD_PA           (0xA1F00000)
#define OMAP2420_SDRAM_LCD_SIZE         (0x01000000)

//------------------------------------------------------------------------------
//  GPMC Module Register base address
//  (see file omap2420_gpmc.h for offset definitions for this base address)
//------------------------------------------------------------------------------

#define OMAP2420_GPMC_REGS_PA           (0x6800A000)

//------------------------------------------------------------------------------
//  SDRAM module register base addresses
//  (see file omap2420_sdram.h for offset definitions for these base addresses)
//------------------------------------------------------------------------------

#define OMAP2420_SMS_REGS_PA            (0x68008000)
#define OMAP2420_SDRC_REGS_PA           (0x68009000)

//
// Frame Adjustment Counter Register (FAC)
// (see file omap24240_timer.h for offset definitions)
//

#define OMAP2420_FAC_REGS_PA            (0x48092000)

//------------------------------------------------------------------------------
//  DSP subsystem (IPI module, dealing with OMAP 24xx memory space) base address
//  (see file omap2420_dsp.h for offset definitions for this base address)
//------------------------------------------------------------------------------

#define OMAP2420_DSP_IPI_REGS_PA        (0x59000000)

//------------------------------------------------------------------------------
//  vlynq module, see file omap2420_vlynq.h for offset definitions for this base address
//------------------------------------------------------------------------------

#define OMAP2420_VLYNQFUNC_REGS_PA      (0x67FFFE00)

//------------------------------------------------------------------------------
//  SSI Controller, see file omap2420_SSI.h for offset definitions
//------------------------------------------------------------------------------

#define OMAP2420_SSI_REGS_PA            (0x48058000)  // SSI controller
#define OMAP2420_GDD1_REGS_PA           (0x48059000)  // Generic distribute DMD port 1
#define OMAP2420_SST1_REGS_PA           (0x4805A000)  // Synchronized serial tranmitter port 1
#define OMAP2420_SSR1_REGS_PA           (0x4805A800)  // Synchronized serial receiver port 1
#define OMAP2420_SST2_REGS_PA           (0x4805B000)  // Synchronized serial transmitter port 2
#define OMAP2420_SSR2_REGS_PA           (0x4805B800)  // Synchronized serial reciever port 2

#define OMAP2420_PRCM_REGS_PA           (0x48008000)

#define OMAP2420_CAMSUB_REGS_PA         (0x48052000) // Camera top
#define OMAP2420_CAMCORE_REGS_PA        (0x48052400) // Camera core
#define OMAP2420_CAMDMA_REGS_PA         (0x48052800) // Camera DMA
#define OMAP2420_CAMMMU_REGS_PA         (0x48052C00) // Camera MMU

#define OMAP2420_GPIO1_REGS_PA          (0x48018000)
#define OMAP2420_GPIO2_REGS_PA          (0x4801A000)
#define OMAP2420_GPIO3_REGS_PA          (0x4801C000)
#define OMAP2420_GPIO4_REGS_PA          (0x4801E000)

#if __cplusplus
}
#endif

#endif