omap3_base_regs.h

Windows CE 6.0 BSP for the Beagle Board.

//
// Copyright (c) Special Computing.  All rights reserved. 
// Copyright (c) Microsoft Corporation.  All rights reserved.
// Copyright (c) Texas Instruments.  All rights reserved. 
//
//------------------------------------------------------------------------------
//
//  Header:  omap3_base_regs.h
//
//  This header file defines the addresses of the base registers for
//  the System on Chip (SoC) components.
//
//  The following abbreviations are used for different addressing type:
//
//                PA - physical address
//                UA - uncached virtual address
//                CA - cached virtual address
//                OA - offset address
//
//  The naming convention for CPU base registers is:
//
//                <SoC>_<SUBSYSTEM>_REGS_<ADDRTYPE>
//
//------------------------------------------------------------------------------
#ifndef __OMAP3_BASE_REGS_H
#define __OMAP3_BASE_REGS_H

#if __cplusplus
extern "C" {
#endif

#define OMAP3_REGS_PA  					(0x48000000)
#define OMAP3_L4_REGS_PA				(0x48000000)
#define OMAP3_L4_REGS_SIZE				(0x08000000)

#define OMAP3_CORE_L4_REGS_PA			OMAP3_REGS_PA
#define OMAP3_WAKEUP_L4_REGS_PA			(OMAP3_REGS_PA+0x00300000)
#define OMAP3_PER_L4_REGS_PA			(OMAP3_REGS_PA+0x01000000)

//------------------------------------------------------------------------------
//  Device ID
//------------------------------------------------------------------------------

#define OMAP3_DEVICE_ID_REGS_PA			(OMAP3_WAKEUP_L4_REGS_PA+0x0000A204)
#define OMAP3_DEVICE_DIEID_REGS_PA		(OMAP3_WAKEUP_L4_REGS_PA+0x0000A218)

//------------------------------------------------------------------------------
//  CORE Configuration
//------------------------------------------------------------------------------

#define OMAP3_CORE_CONFIG_REGS_PA		(OMAP3_CORE_L4_REGS_PA+0x00040000)
#define OMAP3_CORE_AP_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x00040000)
#define OMAP3_CORE_IP_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x00040800)
#define OMAP3_CORE_LA_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x00041000)

//------------------------------------------------------------------------------
//  PER Configuration
//------------------------------------------------------------------------------

#define OMAP3_PER_CONFIG_REGS_PA		(OMAP3_PER_L4_REGS_PA+0x00000000)
#define OMAP3_PER_AP_REGS_PA			(OMAP3_PER_L4_REGS_PA+0x00000000)
#define OMAP3_PER_IP_REGS_PA			(OMAP3_PER_L4_REGS_PA+0x00000800)
#define OMAP3_PER_LA_REGS_PA			(OMAP3_PER_L4_REGS_PA+0x00001000)

//------------------------------------------------------------------------------
//  WAKEUP Configuration
//------------------------------------------------------------------------------

#define OMAP3_WAKEUP_CONFIG_REGS_PA		(OMAP3_WAKUP_L4_REGS_PA+0x00028000)
#define OMAP3_WAKEUP_AP_REGS_PA			(OMAP3_WAKUP_L4_REGS_PA+0x00028000)
#define OMAP3_WAKEUP_IP_REGS_PA			(OMAP3_WAKUP_L4_REGS_PA+0x00028800)
#define OMAP3_WAKEUP_LA_REGS_PA			(OMAP3_WAKUP_L4_REGS_PA+0x00029000)
#define OMAP3_WAKEUP_IP_EMU_REGS_PA		(OMAP3_WAKUP_L4_REGS_PA+0x0002A000)

//------------------------------------------------------------------------------
//  System Control Module (SCM)
//------------------------------------------------------------------------------

#define OMAP3_SCM_REGS_PA				(OMAP3_CORE_L4_REGS_PA+0x00002000)

//------------------------------------------------------------------------------
//  Clock Management module
//------------------------------------------------------------------------------

#define OMAP3_CM_REGS_PA				(OMAP3_CORE_L4_REGS_PA+0x00004000)
#define OMAP3_CM_IVA2_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x00004000)
#define OMAP3_CM_OCP_SYS_REGS_PA		(OMAP3_CORE_L4_REGS_PA+0x00004800)
#define OMAP3_CM_MPU_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x00004900)
#define OMAP3_CM_CORE_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x00004A00)
#define OMAP3_CM_SGX_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x00004B00)
#define OMAP3_CM_WKUP_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x00004C00)
#define OMAP3_CM_CLKCTL_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x00004D00)
#define OMAP3_CM_DSS_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x00004E00)
#define OMAP3_CM_CAM_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x00004F00)
#define OMAP3_CM_PER_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x00005000)
#define OMAP3_CM_EMU_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x00005100)
#define OMAP3_CM_GLOBAL_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x00005200)
#define OMAP3_CM_NEON_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x00005300)
#define OMAP3_CM_USBHOST_REGS_PA		(OMAP3_CORE_L4_REGS_PA+0x00005400)

//------------------------------------------------------------------------------
//  Power and Reset Management module
//------------------------------------------------------------------------------

#define OMAP3_PRM_REGS_PA				(OMAP3_WAKEUP_L4_REGS_PA+0x00006000)
#define OMAP3_PRM_IVA2_REGS_PA			(OMAP3_WAKEUP_L4_REGS_PA+0x00006000)
#define OMAP3_PRM_OCP_SYS_REGS_PA		(OMAP3_WAKEUP_L4_REGS_PA+0x00006800)
#define OMAP3_PRM_MPU_REGS_PA			(OMAP3_WAKEUP_L4_REGS_PA+0x00006900)
#define OMAP3_PRM_CORE_REGS_PA			(OMAP3_WAKEUP_L4_REGS_PA+0x00006A00)
#define OMAP3_PRM_SGX_REGS_PA			(OMAP3_WAKEUP_L4_REGS_PA+0x00006B00)
#define OMAP3_PRM_WKUP_REGS_PA			(OMAP3_WAKEUP_L4_REGS_PA+0x00006C00)
#define OMAP3_PRM_CLKCTL_REGS_PA		(OMAP3_WAKEUP_L4_REGS_PA+0x00006D00)
#define OMAP3_PRM_DSS_REGS_PA			(OMAP3_WAKEUP_L4_REGS_PA+0x00006E00)
#define OMAP3_PRM_CAM_REGS_PA			(OMAP3_WAKEUP_L4_REGS_PA+0x00006F00)
#define OMAP3_PRM_PER_REGS_PA			(OMAP3_WAKEUP_L4_REGS_PA+0x00007000)
#define OMAP3_PRM_EMU_REGS_PA			(OMAP3_WAKEUP_L4_REGS_PA+0x00007100)
#define OMAP3_PRM_GLOBAL_REGS_PA		(OMAP3_WAKEUP_L4_REGS_PA+0x00007200)
#define OMAP3_PRM_NEON_REGS_PA			(OMAP3_WAKEUP_L4_REGS_PA+0x00007300)
#define OMAP3_PRM_USBHOST_REGS_PA		(OMAP3_WAKEUP_L4_REGS_PA+0x00007400)

//------------------------------------------------------------------------------
//  Display Subsystem
//------------------------------------------------------------------------------

#define OMAP3_DISS_REGS_PA				(OMAP3_CORE_L4_REGS_PA+0x00050000)
#define OMAP3_DISPC_REGS_PA				(OMAP3_CORE_L4_REGS_PA+0x00050400)
#define OMAP3_RFBI_REGS_PA				(OMAP3_CORE_L4_REGS_PA+0x00050800)
#define OMAP3_VENC_REGS_PA				(OMAP3_CORE_L4_REGS_PA+0x00050C00)

//------------------------------------------------------------------------------
//  System DMA (SDMA aka DMA4)
//------------------------------------------------------------------------------

#define OMAP3_SDMA_REGS_PA				(OMAP3_CORE_L4_REGS_PA+0x00056000)
#define OMAP3_DMA4_REGS_PA				(OMAP3_CORE_L4_REGS_PA+0x00056000)

//------------------------------------------------------------------------------
//  I2C Controller
//------------------------------------------------------------------------------

#define OMAP3_I2C1_REGS_PA				(OMAP3_CORE_L4_REGS_PA+0x00070000)
#define OMAP3_I2C2_REGS_PA				(OMAP3_CORE_L4_REGS_PA+0x00072000)
#define OMAP3_I2C3_REGS_PA				(OMAP3_CORE_L4_REGS_PA+0x00060000)

//------------------------------------------------------------------------------
//  UART Units
//------------------------------------------------------------------------------

#define OMAP3_UART1_REGS_PA				(OMAP3_CORE_L4_REGS_PA+0x0006A000)
#define OMAP3_UART2_REGS_PA				(OMAP3_CORE_L4_REGS_PA+0x0006C000)
#define OMAP3_UART3_REGS_PA				(OMAP3_PER_L4_REGS_PA+0x00020000)

//------------------------------------------------------------------------------
//  USB Host
//------------------------------------------------------------------------------

#define OMAP3_USB_HS_TTL_REG_PA			(OMAP3_CORE_L4_REGS_PA+0x00062000)
#define OMAP3_USB_HS_HOST_REG_PA		(OMAP3_CORE_L4_REGS_PA+0x00064000)

//------------------------------------------------------------------------------
//  USB OTG
//------------------------------------------------------------------------------

#define OMAP3_USB_HS_OTG_REG_PA			(OMAP3_CORE_L4_REGS_PA+0x000AB000)

//------------------------------------------------------------------------------
//  McBSP
//------------------------------------------------------------------------------

#define OMAP3_MCBSP1_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x00074000)
#define OMAP3_MCBSP2_REGS_PA			(OMAP3_PER_L4_REGS_PA+0x00022000)
#define OMAP3_MCBSP3_REGS_PA			(OMAP3_PER_L4_REGS_PA+0x00024000)
#define OMAP3_MCBSP4_REGS_PA			(OMAP3_PER_L4_REGS_PA+0x00026000)
#define OMAP3_MCBSP5_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x00096000)
#define OMAP3_MCBSP2_SIDETONE_REGS_PA	(OMAP3_PER_L4_REGS_PA+0x00028000)
#define OMAP3_MCBSP3_SIDETONE_REGS_PA	(OMAP3_PER_L4_REGS_PA+0x00029000)

//------------------------------------------------------------------------------
//  McSPI
//------------------------------------------------------------------------------

#define OMAP3_MCSPI1_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x00098000)
#define OMAP3_MCSPI2_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x0009A000)
#define OMAP3_MCSPI3_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x000B8000)
#define OMAP3_MCSPI4_REGS_PA			(OMAP3_CORE_L4_REGS_PA+0x000BA000)

//------------------------------------------------------------------------------
//  SmartReflex
//------------------------------------------------------------------------------

#define OMAP3_SR1_REG_PA				(OMAP3_CORE_L4_REGS_PA+0x000C9000)
#define OMAP3_SR2_REG_PA				(OMAP3_CORE_L4_REGS_PA+0x000CA000)

//------------------------------------------------------------------------------