omap3_mcspi.h

Windows CE 6.0 BSP for the Beagle Board.

//
// Copyright (c) Special Computing.  All rights reserved. 
// Copyright (c) Microsoft Corporation.  All rights reserved.
// Copyright (c) Texas Instruments.  All rights reserved. 
//
//------------------------------------------------------------------------------
//
//  Header:  omap3_mcspi.h
//
//  This header file is comprised of McBSP module register details defined as 
//  structures and macros for configuring and controlling McBSP module
//
//------------------------------------------------------------------------------
#ifndef __OMAP3_MCSPI_H
#define __OMAP3_MCSPI_H

#if __cplusplus
extern "C" {
#endif

//------------------------------------------------------------------------------
// Base Address : OMAP3_MCSPI1_REGS_PA
//				  OMAP3_MCSPI2_REGS_PA
//				  OMAP3_MCSPI3_REGS_PA
//				  OMAP3_MCSPI4_REGS_PA
//------------------------------------------------------------------------------

typedef volatile struct
{
	UINT32 ulMCSPI_RESERVED_00;		//offset 0x00,
	UINT32 ulMCSPI_RESERVED_04;		//offset 0x04,
	UINT32 ulMCSPI_RESERVED_08;		//offset 0x08,
	UINT32 ulMCSPI_RESERVED_0C;		//offset 0x0C,
	UINT32 ulMCSPI_SYSCONFIG;		//offset 0x10, System config
	UINT32 ulMCSPI_SYSSTATUS;		//offset 0x14, System status
	UINT32 ulMCSPI_IRQSTATUS;		//offset 0x18, IRQ status
	UINT32 ulMCSPI_IRQENABLE;		//offset 0x1C, IRQ enable
	UINT32 ulMCSPI_WAKEUPENABLE;	//offset 0x20, WKUP enable
	UINT32 ulMCSPI_SYST;			//offset 0x24, System test 
	UINT32 ulMCSPI_MODULCTRL;		//offset 0x28, SPI config
	UINT32 ulMCSPI_CH0CONF;			//offset 0x2C, Channel 0 config
	UINT32 ulMCSPI_CH0STATUS;		//offset 0x30, Channel 0 status
	UINT32 ulMCSPI_CH0CTRL;			//offset 0x34, Channel 0 control
	UINT32 ulMCSPI_TX0;				//offset 0x38, Transmit0 register
	UINT32 ulMCSPI_RX0;				//offset 0x3C, Receive0 register         
	UINT32 ulMCSPI_CH1CONF;			//offset 0x40, Channel 1 config
	UINT32 ulMCSPI_CH1STATUS;		//offset 0x44, Channel 1 status
	UINT32 ulMCSPI_CH1CTRL;			//offset 0x48, Channel 1 control
	UINT32 ulMCSPI_TX1;				//offset 0x4C, Transmit1 register
	UINT32 ulMCSPI_RX1;				//offset 0x50, Receive 1 register
	UINT32 ulMCSPI_CH2CONF;			//offset 0x54,
	UINT32 ulMCSPI_CH2STATUS;		//offset 0x58, Channel 2 status
	UINT32 ulMCSPI_CH2CTRL;			//offset 0x5C, Channel 2 control
	UINT32 ulMCSPI_TX2;				//offset 0x60, Transmit2 register
	UINT32 ulMCSPI_RX2;				//offset 0x64, Receive2 register   
	UINT32 ulMCSPI_CH3CONF;			//offset 0x68,
	UINT32 ulMCSPI_CH3STATUS;		//offset 0x6C, Channel 3 status
	UINT32 ulMCSPI_CH3CTRL;			//offset 0x70, Channel 3 control
	UINT32 ulMCSPI_TX3;				//offset 0x74, Transmit3 register
	UINT32 ulMCSPI_RX3;				//offset 0x78, Receive3 register
	UINT32 ulMCSPI_XFERLEVEL;		//offset 0x7C, Transfer level
}
OMAP3_MCSPI_REGS;

//------------------------------------------------------------------------------

#define MCSPI_SYSCONFIG_SRST		(1 << 1)

#if __cplusplus
}
#endif

#endif