omap2420_display.h

Windows CE 6.0 BSP for the Beagle Board.

#define DSS_CONTROL_DAC_LCDPSAON				(1 << 7)
#define DSS_CONTROL_DAC_VIDEOPSACLR				(1 << 8)
#define DSS_CONTROL_DAC_VIDEOPSAON				(1 << 9)

// DSS_PSA_LCD_REG_2 register fields

#define DSS_PSA_LCD_2_SIG_MSB(sig)				((sig) << 0)
#define DSS_PSA_LCD_2_DATA_AVAIL				(1 << 31)

// DSS_PSA_VIDEO_REG register fields

#define DSS_PSA_VIDEO_SIG(sig)					((sig) << 0)
#define DSS_PSA_VIDEO_DATA_AVAIL				(1 << 31)

// DSS_STATUS register fields

#define DSS_STATUS_DPLL_ENABLE					(1 << 0)
#define DSS_STATUS_APLL_ENABLE					(1 << 1)

// DISPC_SYSCONFIG register fields

#define DISPC_SYSCONFIG_AUTOIDLE				(1 << 0)
#define DISPC_SYSCONFIG_SOFTRESET				(1 << 1)
#define DISPC_SYSCONFIG_SIDLEMODE(mode)			((mode) << 3)
#define DISPC_SYSCONFIG_MIDLEMODE(mode)			((mode) << 12)

// DISPC_SYSSTATUS register fields

#define DISPC_SYSSTATUS_RESETDONE				(1 << 0)

// DISPC_CONTROL register fields

#define DISPC_CONTROL_LCDENABLE					(1 << 0)
#define DISPC_CONTROL_DIGITALENABLE				(1 << 1)
#define DISPC_CONTROL_MONCOLOR					(1 << 2)
#define DISPC_CONTROL_STNTFT					(1 << 3)
#define DISPC_CONTROL_M8B						(1 << 4)
#define DISPC_CONTROL_GOLCD						(1 << 5)
#define DISPC_CONTROL_GODIGITAL					(1 << 6)
#define DISPC_CONTROL_TFTDITHER_ENABLE			(1 << 7)
#define DISPC_CONTROL_TFTDATALINES_12			(0 << 8)
#define DISPC_CONTROL_TFTDATALINES_16			(1 << 8)
#define DISPC_CONTROL_TFTDATALINES_18			(2 << 8)
#define DISPC_CONTROL_TFTDATALINES_24			(3 << 8)
#define DISPC_CONTROL_SECURE					(1 << 10)
#define DISPC_CONTROL_RFBIMODE					(1 << 11)
#define DISPC_CONTROL_OVERLAY_OPTIMIZATION		(1 << 12)
#define DISPC_CONTROL_GPOUT0					(1 << 15)
#define DISPC_CONTROL_GPOUT1					(1 << 16)
#define DISPC_CONTROL_HT(ht)					((ht) << 17)
#define DISPC_CONTROL_TDMENABLE					(1 << 20)
#define DISPC_CONTROL_TDMPARALLEL_MODE_8		(0 << 21)
#define DISPC_CONTROL_TDMPARALLEL_MODE_9		(1 << 21)
#define DISPC_CONTROL_TDMPARALLEL_MODE_12		(2 << 21)
#define DISPC_CONTROL_TDMPARALLEL_MODE_16		(3 << 21)
#define DISPC_CONTROL_TDMCYCLE_FORMAT_11		(0 << 23)
#define DISPC_CONTROL_TDMCYCLE_FORMAT_21		(1 << 23)
#define DISPC_CONTROL_TDMCYCLE_FORMAT_31		(2 << 23)
#define DISPC_CONTROL_TDMCYCLE_FORMAT_32		(3 << 23)
#define DISPC_CONTROL_TDMUNUSED_BITS_LO			(0 << 25)
#define DISPC_CONTROL_TDMUNUSED_BITS_HI			(1 << 25)
#define DISPC_CONTROL_TDMUNUSED_BITS_SAME		(2 << 25)

// DISPC_CONFIG register fields

#define DISPC_CONFIG_PIXELGATED					(1 << 0)
#define DISPC_CONFIG_LOADMODE(mode)				((mode) << 1)
#define DISPC_CONFIG_PALETTEGAMMATABLE			(1 << 3)
#define DISPC_CONFIG_PIXELDATAGATED				(1 << 4)
#define DISPC_CONFIG_PIXELCLOCKGATED			(1 << 5)
#define DISPC_CONFIG_HSYNCGATED					(1 << 6)
#define DISPC_CONFIG_VSYNCGATED					(1 << 7)
#define DISPC_CONFIG_ACBIASGATED				(1 << 8)
#define DISPC_CONFIG_FUNCGATED					(1 << 9)
#define DISPC_CONFIG_TCKLCDENABLE				(1 << 10)
#define DISPC_CONFIG_TCKLCDSELECTION			(1 << 11)
#define DISPC_CONFIG_TCKDIGENABLE				(1 << 12)
#define DISPC_CONFIG_TCKDIGSELECTION			(1 << 13)

// DISPC_TIMING_H register fields

#define DISPC_TIMING_H_HSW(hsw)					(((hsw) - 1) << 0)
#define DISPC_TIMING_H_HFP(hfp)					(((hfp) - 1) << 8)
#define DISPC_TIMING_H_HBP(hbp)					(((hbp) - 1) << 20)

// DISPC_TIMING_V register fields

#define DISPC_TIMING_V_HSW(vsw)					((vsw) << 0)
#define DISPC_TIMING_V_HFP(vfp)					((vfp) << 8)
#define DISPC_TIMING_V_HBP(vbp)					((vbp) << 20)

// DISPC_POL_FREQ register fields

#define DISPC_POL_FREQ_ACB(acb)					((acb) << 0)
#define DISPC_POL_FREQ_ACBI(acbi)				((acbi) << 8)
#define DISPC_POL_FREQ_IVS						(1 << 12)
#define DISPC_POL_FREQ_IHS						(1 << 13)
#define DISPC_POL_FREQ_IPC						(1 << 14)
#define DISPC_POL_FREQ_IEO						(1 << 15)
#define DISPC_POL_FREQ_RF						(1 << 16)
#define DISPC_POL_FREQ_ONOFF					(1 << 17)

// DISPC_DIVISOR register fields

#define DISPC_DIVISOR_PCD(pcd)					((pcd) << 0)
#define DISPC_DIVISOR_LCD(lcd)					((lcd) << 16)

// DISPC_SIZE_DIG register fields

#define DISPC_SIZE_DIG_PPL(ppl)					(((ppl) - 1) << 0)
#define DISPC_SIZE_DIG_LPP(lpp)					(((lpp) - 1) << 16)

// DISPC_SIZE_LCD register fields

#define DISPC_SIZE_LCD_PPL(ppl)					(((ppl) - 1) << 0)
#define DISPC_SIZE_LCD_LPP(lpp)					(((lpp) - 1) << 16)

// DISPC_GFX_POSITION register fields

#define DISPC_GFX_POS_GFXPOSX(x)				((x) << 0)
#define DISPC_GFX_POS_GFXPOSY(y)				((y) << 16)

// DISPC_GFX_SIZE register fields

#define DISPC_GFX_SIZE_GFXSIZEX(x)				(((x) - 1) << 0)
#define DISPC_GFX_SIZE_GFXSIZEY(y)				(((y) - 1) << 16)

// DISPC_GFX_ATTRIBUTES register fields

#define DISPC_GFX_ATTR_GFXENABLE				(1 << 0)
#define DISPC_GFX_ATTR_GFXFORMAT(fmt)			((fmt) << 1)
#define DISPC_GFX_ATTR_GFXREPLICATIONENABLE		(1 << 5)
#define DISPC_GFX_ATTR_GFXBURSTSIZE(burst)		((burst) << 6)
#define DISPC_GFX_ATTR_GFXCHANNELOUT			(1 << 8)
#define DISPC_GFX_ATTR_GFXNIBBLEMODE			(1 << 9)
#define DISPC_GFX_ATTR_GFXENDIANESS				(1 << 10)

// DISPC_GFX_FIFO_THRESHOLD register fields

#define DISPC_GFX_FIFO_THRESHOLD_LOW(low)		((low) << 0)
#define DISPC_GFX_FIFO_THRESHOLD_HIGH(high)		((high) << 16)

// DISPC_VID1_POSITION and DISPC_VID2_POSITION register fields

#define DISPC_VID_POS_VIDPOSX(x)				((x) << 0)
#define DISPC_VID_POS_VIDPOSY(y)				((y) << 16)

// DISPC_VID1_SIZE and DISPC_VID2_SIZE register fields

#define DISPC_VID_SIZE_VIDSIZEX(x)				(((x) - 1) << 0)
#define DISPC_VID_SIZE_VIDSIZEY(y)				(((y) - 1) << 16)

// DISPC_VID1_ATTRIBUTES and DISPC_VID2_ATTRIBUTES register fields

#define DISPC_VID_ATTR_VIDENABLE				(1 << 0)
#define DISPC_VID_ATTR_VIDFORMAT(fmt)			((fmt) << 1)
#define DISPC_VID_ATTR_VIDRESIZE_NONE			(0 << 5)
#define DISPC_VID_ATTR_VIDRESIZE_HORIZONTAL		(1 << 5)
#define DISPC_VID_ATTR_VIDRESIZE_VERTICAL		(2 << 5)
#define DISPC_VID_ATTR_VIDRESIZE_BOTH			(3 << 5)
#define DISPC_VID_ATTR_VIDHRESIZE_CONF			(1 << 7)
#define DISPC_VID_ATTR_VIDVRESIZE_CONF			(1 << 8)
#define DISPC_VID_ATTR_VIDCOLORCONVENABLE		(1 << 9)
#define DISPC_VID_ATTR_VIDREPLICATIONENABLE		(1 << 10)
#define DISPC_VID_ATTR_VIDFULLRANGE				(1 << 11)
#define DISPC_VID_ATTR_VIDROTATION_0			(1 << 12)
#define DISPC_VID_ATTR_VIDROTATION_90			(1 << 12)
#define DISPC_VID_ATTR_VIDROTATION_180			(1 << 12)
#define DISPC_VID_ATTR_VIDROTATION_270			(1 << 12)
#define DISPC_VID_ATTR_VIDBURSTSIZE(burst)		((burst) << 14)
#define DISPC_VID_ATTR_VIDCHANNELOUT			(1 << 16)
#define DISPC_VID_ATTR_VIDENDIANNESS			(1 << 17)
#define DISPC_VID_ATTR_VIDROWREPEATENABLE		(1 << 18)

// DISPC_VID1_FIFO_THRESHOLD and DISPC_VID2_FIFO_THRESHOLD register fields

#define DISPC_VID_FIFO_THRESHOLD_LOW(low)		((low) << 0)
#define DISPC_VID_FIFO_THRESHOLD_HIGH(high)		((high) << 16)

// DISPC_VID1_PICTURE_SIZE and DISPC_VID2_PICTURE_SIZE register fields

#define DISPC_VID_PICTURE_SIZE_VIDORGSIZEX(x)	(((x) - 1) << 0)
#define DISPC_VID_PICTURE_SIZE_VIDORGSIZEY(y)	(((y) - 1) << 16)

// DISPC_VID1_FIR and DISPC_VID2_FIR register fields

#define DISPC_VID_FIR_VIDFIRHINC(inc)			((inc) << 0)
#define DISPC_VID_FIR_VIDFIRVINC(inc)			((inc) << 16)

// DISPC_VID1_CONV_COEF0 and DISPC_VID2_CONV_COEF0 register fields

#define DISPC_VID_CONV_COEF0_RY(ry)				((ry) << 0)
#define DISPC_VID_CONV_COEF0_RCR(rcr)			((rcr) << 16)

// DISPC_VID1_CONV_COEF1 and DISPC_VID2_CONV_COEF1 register fields

#define DISPC_VID_CONV_COEF1_RCB(rcb)			((rcb) << 0)
#define DISPC_VID_CONV_COEF1_GY(gy)				((gy) << 16)

// DISPC_VID1_CONV_COEF2 and DISPC_VID2_CONV_COEF2 register fields

#define DISPC_VID_CONV_COEF2_GCR(gcr)			((gcr) << 0)
#define DISPC_VID_CONV_COEF2_GCB(gcb)			((gcb) << 16)

// DISPC_VID1_CONV_COEF3 and DISPC_VID2_CONV_COEF3 register fields

#define DISPC_VID_CONV_COEF3_BY(by)				((by) << 0)
#define DISPC_VID_CONV_COEF3_BCR(bcr)			((bcr) << 16)

// DISPC_VID1_CONV_COEF4 and DISPC_VID2_CONV_COEF4 register fields

#define DISPC_VID_CONV_COEF4_BCB(bcb)			((bcb) << 0)

// DISPC_DAC_TST register fields

#define DISPC_DAC_TST_DACX						(1 << 1)
#define DISPC_DAC_TST_DAC_INVT					(1 << 3)
#define DISPC_DAC_TST_DAC_DX					(1 << 4)
#define DISPC_DAC_TST_DAC_SEL					(1 << 6)

//DISPC_IRQSTATUS

#define DISPC_IRQSTATUS_FRAMEDONE               (1 << 0)
#define DISPC_IRQSTATUS_VSYNC                   (1 << 1)
#define DISPC_IRQSTATUS_EVSYNC_EVEN             (1 << 2)
#define DISPC_IRQSTATUS_EVSYNCODD               (1 << 3)
#define DISPC_IRQSTATUS_ACBIASCOUNTSTATUS       (1 << 4)
#define DISPC_IRQSTATUS_PROGRAMMEDLINENUMBER    (1 << 5)
#define DISPC_IRQSTATUS_GFXFIFOUNDERFLOW        (1 << 6)
#define DISPC_IRQSTATUS_GFXENDWINDOW            (1 << 7)
#define DISPC_IRQSTATUS_PALLETEGAMMALOADING     (1 << 8)
#define DISPC_IRQSTATUS_OCPERROR                (1 << 9)
#define DISPC_IRQSTATUS_VID1FIFOUNDERFLOW       (1 << 10)
#define DISPC_IRQSTATUS_VID1ENDWINDOW           (1 << 11)
#define DISPC_IRQSTATUS_VID2FIFOUNDERFLOW       (1 << 12)
#define DISPC_IRQSTATUS_VID2ENDWINDOW           (1 << 13)
#define DISPC_IRQSTATUS_SYNCLOST                (1 << 14)
#define DISPC_IRQSTATUS_SYNCLOSTDIGITAL         (1 << 15)

#endif