omap2420_display.h

Windows CE 6.0 BSP for the Beagle Board.

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this sample source code is subject to the terms of the Microsoft
// license agreement under which you licensed this sample source code. If
// you did not accept the terms of the license agreement, you are not
// authorized to use this sample source code. For the terms of the license,
// please see the license agreement between you and Microsoft or, if applicable,
// see the LICENSE.RTF on your install media or the root of your tools installation.
// THE SAMPLE SOURCE CODE IS PROVIDED "AS IS", WITH NO WARRANTIES.
//
//
// Portions Copyright (c) Texas Instruments.  All rights reserved. 
//
//------------------------------------------------------------------------------
//
//  File:  omap2420_display.h
//
//  This header file is comprised of display module register details defined as
// structures and macros for configuring and controlling display module

#ifndef __OMAP2420_DISPLAY_H
#define __OMAP2420_DISPLAY_H

//------------------------------------------------------------------------------

//
// Display Subsystem Specific (DSS)
//

// Base Address: OMAP2420_DISS1_REGS_PA

typedef volatile struct
{
	UINT32 ulDSS_REVISIONNUMBER;	//offset 0x00, Revision ID
	UINT32 ulRESERVED_1[3];
	UINT32 ulDSS_SYSCONFIG;			//offset 0x10, OCP i/f params
	UINT32 ulDSS_SYSSTATUS;			//offset 0x14, module status info
	UINT32 ulRESERVED_2[10];
	UINT32 ulDSS_CONTROL;			//offset 0x40, DSS control bits
	UINT32 ulRESERVED_3[3];
	UINT32 ulDSS_PSA_LCD_REG1;		//offset 0x50, PSA LCD 32 LSB signature
	UINT32 ulDSS_PSA_LCD_REG2;		//offset 0x54, PSA LCD 32 MSB signature
	UINT32 ulDSS_PSA_VIDEO_REG;		//offset 0x58, PSA video signature and data availability
	UINT32 ulDSS_STATUS;			//offset 0x5C, DSS status
}
OMAP2420_DSS_REGS;

typedef volatile struct
{
	UINT32 ulH;
	UINT32 ulHV;
}
OMAP2420_FIRCOEF_REGS;

typedef volatile struct
{
	UINT32 ulBA0;				//offset 0x00, base addr config of vid buf0 for video win #n
	UINT32 ulBA1;				//offset 0x04, base addr config of vid buf1 for video win #n
	UINT32 ulPOSITION;			//offset 0x08, pos of vid win #n
	UINT32 ulSIZE;				//offset 0x0C, size of vid win #n
	UINT32 ulATTRIBUTES;		//offset 0x10, config of vid win #n
	UINT32 ulFIFO_THRESHOLD;	//offset 0x14, video FIFO associated with video pipeline #n
	UINT32 ulFIFO_SIZE_STATUS;	//offset 0x18, GFX FIFO size status
	UINT32 ulROW_INC;			//offset 0x1C, no of bytes to inc at end of row
	UINT32 ulPIXEL_INC;			//offset 0x20, no of bytes to incr bet 2 pixels
	UINT32 ulFIR;				//offset 0x24, resize factors for horz & vert up/down sampling of video win #n
	UINT32 ulPICTURE_SIZE;		//offset 0x28, video pict size conf 
	UINT32 ulACCU0;				//offset 0x2C, configures resize accumulator init values for horz and vert up/dn-sampling
	UINT32 ulACCU1;				//offset 0x30, configures resize accumulator init values for horz and vert up/dn-sampling
	OMAP2420_FIRCOEF_REGS aFIR_COEF[8];	// offset 0x34, configures up/dn-scaling coeff for vert & horz resize
										// of video pict asso with video win #n for the phase i
	UINT32 ulCONV_COEF0;		//offset 0x74, color space conversion matrix coeff
	UINT32 ulCONV_COEF1;		//offset 0x78, color space conversion matrix coeff
	UINT32 ulCONV_COEF2;		//offset 0x7C, color space conversion matrix coeff
	UINT32 ulCONV_COEF3;		//offset 0x80, color space conversion matrix coeff
	UINT32 ulCONV_COEF4;		//offset 0x84, color space conversion matrix coeff
}
OMAP2420_VID_REGS;

typedef volatile struct
{
	UINT32 ulDISPC_REVISION;			//offset 0x0, revision code
	UINT32 ulRESERVED_1[3];
	UINT32 ulDISPC_SYSCONFIG;			//offset 0x10, OCP i/f params
	UINT32 ulDISPC_SYSSTATUS;			//offset 0x14, module status info
	UINT32 ulDISPC_IRQSTATUS;			//offset 0x18, module internal events status
	UINT32 ulDISPC_IRQENABLE;			//offset 0x1C, module intr mask/unmask
	UINT32 ulRESERVED_2[8];
	UINT32 ulDISPC_CONTROL;				//offset 0x40, module configuration
	UINT32 ulDISPC_CONFIG;				//offset 0x44, shadow reg updated on VFP start period
	UINT32 ulDISPC_CAPABLE;				//offset 0x48, shadow reg updated on VFP start period
	UINT32 ulDISPC_DEFAULT_COLOR0;		//offset 0x4C, def solid bkgrnd color config
	UINT32 ulDISPC_DEFAULT_COLOR1;		//offset 0x50, def solid bkgrnd color config
	UINT32 ulDISPC_TRANS_COLOR0;		//offset 0x54, def trans colorvalue for video/graphics
	UINT32 ulDISPC_TRANS_COLOR1;		//offset 0x58, def trans colorvalue for video/graphics
	UINT32 ulDISPC_LINE_STATUS;			//offset 0x5C, current LCD panel display line number
	UINT32 ulDISPC_LINE_NUMBER;			//offset 0x60, LCD panel display line number for  intr&DMA req
	UINT32 ulDISPC_TIMING_H;			//offset 0x64, timing logic for HSYNC signal
	UINT32 ulDISPC_TIMING_V;			//offset 0x68, timing logic for VSYNC signal
	UINT32 ulDISPC_POL_FREQ;			//offset 0x6C, signal config
	UINT32 ulDISPC_DIVISOR;				//offset 0x70, divisor config
	UINT32 ulRESERVED_3;
	UINT32 ulDISPC_SIZE_DIG;			//offset 0x78, configures frame, size of digital o/p field
	UINT32 ulDISPC_SIZE_LCD;			//offset 0x7C, configure panel size
	UINT32 ulDISPC_GFX_BA0;				//offset 0x80, base addr of GFX buf
	UINT32 ulDISPC_GFX_BA1;				//offset 0x84, base addr of GFX buf
	UINT32 ulDISPC_GFX_POSITION;		//offset 0x88, config posof GFX win
	UINT32 ulDISPC_GFX_SIZE;			//offset 0x8C, size of GFX window
	UINT32 ulRESERVED_4[4];
	UINT32 ulDISPC_GFX_ATTRIBUTES;		//offset 0xA0, config attr of GFX
	UINT32 ulDISPC_GFX_FIFO_THRESHOLD;	//offset 0xA4, GFX FIFO config
	UINT32 ulDISPC_GFX_FIFO_SIZE_STATUS;//offset 0xA8, GFX FIFO size status
	UINT32 ulDISPC_GFX_ROW_INC;			//offset 0xAC, no of bytes to inc at end of row.
	UINT32 ulDISPC_GFX_PIXEL_INC;		//offset 0xB0, no of bytes to incr bet 2 pixels
	UINT32 ulDISPC_GFX_WINDOW_SKIP;		//offset 0xB4, no of bytes to skip during video win#n disp
	UINT32 ulDISPC_GFX_TABLE_BA;		//offset 0xB8, config base addr of palette buffer or the gamma tbl buf
	OMAP2420_VID_REGS tDISPC_VID1;		//offset 0xBC, video1 pipeline registers
	UINT32 ulRESERVED_5[2];
	OMAP2420_VID_REGS tDISPC_VID2;		//offset 0x14C, video2 pipeline registers
	UINT32 ulDISPC_DATA_CYCLE1;			//offset 0x1D4, color space conversion matrix coeff
	UINT32 ulDISPC_DATA_CYCLE2;			//offset 0x1D8, color space conversion matrix coeff
	UINT32 ulDISPC_DATA_CYCLE3;			//offset 0x1DC, color space conversion matrix coeff
}
OMAP2420_DISPC_REGS;

//
// Remote Frame Buffer
//

// Base Address: OMAP2420_RFBI1_REGS_PA (defined as 0x48050800)
   
typedef volatile struct
{
	UINT32 ulRFBI_REVISION;			//offset 0x0, revision ID
	UINT32 ulRESERVED_1[3];
	UINT32 ulRFBI_SYSCONFIG;		//offset 0x10, OCP i/f control
	UINT32 ulRFBI_SYSSTATUS;		//offset 0x14, status information
	UINT32 ulRESERVED_2[10];
	UINT32 ulRFBI_CONTROL;			//offset 0x40, module config
	UINT32 ulRFBI_PIXEL_CNT;		//offset 0x44, pixel cnt value
	UINT32 ulRFBI_LINE_NUMBER;		//offset 0x48, no of lines to sync the beginning of transfer
	UINT32 ulRFBI_CMD;				//offset 0x4C, cmd config
	UINT32 ulRFBI_PARAM;			//offset 0x50, parms config
	UINT32 ulRFBI_DATA;				//offset 0x54, data config
	UINT32 ulRFBI_READ;				//offset 0x58, read config
	UINT32 ulRFBI_STATUS;			//offset 0x5C, status config
	UINT32 ulRFBI_CONFIG0;			//offset 0x60, config0 module
	UINT32 ulRFBI_ONOFF_TIME0;		//offset 0x64, timing config
	UINT32 ulRFBI_CYCLE_TIME0;		//offset 0x68, timing config
	UINT32 ulRFBI_DATA_CYCLE1_0;	//offset 0x6C, data format for 1st cycle
	UINT32 ulRFBI_DATA_CYCLE2_0;	//offset 0x70, data format for 2nd cycle
	UINT32 ulRFBI_DATA_CYCLE3_0;	//offset 0x74, data format for 3rd cycle
	UINT32 ulRFBI_CONFIG1;			//offset 0x78, config1 module
	UINT32 ulRFBI_ONOFF_TIME1;		//offset 0x7C, timing config
	UINT32 ulRFBI_CYCLE_TIME1;		//offset 0x80, timing config
	UINT32 ulRFBI_DATA_CYCLE1_1;	//offset 0x84, data format for 1st cycle
	UINT32 ulRFBI_DATA_CYCLE2_1;	//offset 0x88, data format for 2nd cycle
	UINT32 ulRFBI_DATA_CYCLE3_1;	//offset 0x8C, data format for 3rd cycle
	UINT32 ulRFBI_VSYNC_WIDTH;		//offset 0x90, VSYNC min pulse
	UINT32 ulRFBI_HSYNC_WIDTH;		//offset 0x94, HSYNC max pulse
}
OMAP2420_RFBI_REGS, *pRFBIREGS;

//
// Video Encoder  - TBD
//
// Base Address: OMAP2420_VENC1_REGS_PA (defined as 0x48050C00)
   
typedef volatile struct
{
	UINT32 ulVENC_REV_ID;							//offset 0x00
	UINT32 ulVENC_STATUS;							//offset 0x04
	UINT32 ulVENC_F_CONTROL;						//offset 0x08
	UINT32 ulVENC_ulRESERVED_1;						//offset 0x0C
	UINT32 ulVENC_VIDOUT_CTRL;						//offset 0x10 
	UINT32 ulVENC_SYNC_CTRL;						//offset 0x14
	UINT32 ulVENC_ulRESERVED_2;						//offset 0x18
	UINT32 ulVENC_LLEN;								//offset 0x1C
	UINT32 ulVENC_FLENS;							//offset 0x20
	UINT32 ulVENC_HFLTR_CTRL;						//offset 0x24
	UINT32 ulVENC_CC_CARR_WSS_CARR;					//offset 0x28
	UINT32 ulVENC_C_PHASE;							//offset 0x2C
	UINT32 ulVENC_GAIN_U;							//offset 0x30
	UINT32 ulVENC_GAIN_V;							//offset 0x34
	UINT32 ulVENC_GAIN_Y;							//offset 0x38
	UINT32 ulVENC_BLACK_LEVEL;						//offset 0x3C
	UINT32 ulVENC_BLANK_LEVEL;						//offset 0x40
	UINT32 ulVENC_X_COLOR;							//offset 0x44
	UINT32 ulVENC_M_CONTROL;						//offset 0x48
	UINT32 ulVENC_BSTAMP_WSS_DATA;					//offset 0x4C
	UINT32 ulVENC_S_CARR;							//offset 0x50
	UINT32 ulVENC_LINE21;							//offset 0x54
	UINT32 ulVENC_LN_SEL;							//offset 0x58
	UINT32 ulVENC_L21__WC_CTL;						//offset 0x5C
	UINT32 ulVENC_HTRIGGER_VTRIGGER;				//offset 0x60
	UINT32 ulVENC_SAVID__EAVID;						//offset 0x64
	UINT32 ulVENC_FLEN__FAL;						//offset 0x68
	UINT32 ulVENC_LAL__PHASE_RESET;					//offset 0x6C
	UINT32 ulVENC_HS_INT_START_STOP_X;				//offset 0x70
	UINT32 ulVENC_HS_EXT_START_STOP_X;				//offset 0x74
	UINT32 ulVENC_VS_INT_START_X;					//offset 0x78
	UINT32 ulVENC_VS_INT_STOP_X__VS_INT_START_Y;	//offset 0x7C
	UINT32 ulVENC_VS_INT_STOP_Y__VS_EXT_START_X;	//offset 0x80
	UINT32 ulVENC_VS_EXT_STOP_X__VS_EXT_START_Y;	//offset 0x84
	UINT32 ulVENC_VS_EXT_STOP_Y;					//offset 0x88
	UINT32 ulVENC_ulRESERVED_3;						//offset 0x8C
	UINT32 ulVENC_AVID_START_STOP_X;				//offset 0x90
	UINT32 ulVENC_AVID_START_STOP_Y;				//offset 0x94
	UINT32 ulVENC_ulRESERVED_4[2];					//offset 0x98
	UINT32 ulVENC_FID_INT_START_X__FID_INT_START_Y;	//offset 0xA0
	UINT32 ulVENC_FID_INT_OFFSET_Y__FID_EXT_START_X;//offset 0xA4
	UINT32 ulVENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y;//offset 0xA8
	UINT32 ulVENC_ulRESERVED_5;						//offset 0xAC
	UINT32 ulVENC_TVDETGP_INT_START_STOP_X;			//offset 0xB0
	UINT32 ulVENC_TVDETGP_INT_START_STOP_Y;			//offset 0xB4
	UINT32 ulVENC_GEN_CTRL;							//offset 0xB8
	UINT32 ulVENC_ulRESERVED_6;						//offset 0xBC
	UINT32 ulVENC_ulRESERVED_7;						//offset 0xC0
	UINT32 ulVENC_DAC_TST;							//offset 0xC4
	UINT32 ulVENC_DAC;								//offset 0xC8
}
OMAP2420_VENC_REGS, *pVENCREGS;

// DSS_SYSCONFIG register fields

#define DSS_SYSCONFIG_AUTOIDLE					(1 << 0)
#define DSS_SYSCONFIG_SOFTRESET					(1 << 1)

// DSS_SYSSTATUS register fields

#define DSS_SYSSTATUS_RESETDONE					(1 << 0)

// DSS_CONTROL register fields

#define DSS_CONTROL_DPLL_APLL_CLK				(1 << 0)
#define DSS_CONTROL_RESERVED1					(1 << 1)
#define DSS_CONTROL_VENC_CLOCK_MODE				(1 << 2)
#define DSS_CONTROL_VENC_CLOCK_4X_ENABLE		(1 << 3)
#define DSS_CONTROL_DAC_DEMEN					(1 << 4)
#define DSS_CONTROL_DAC_LCDPSACLR				(1 << 6)