omap2420_dma.h

Windows CE 6.0 BSP for the Beagle Board.

#define SDMA_REQ_MS						63
#define SDMA_REQ_UNCONNECTED_64			64

//------------------------------------------------------------------------------
// DSP DMA request mappings

#define DDMA_REQ_XTI					1
#define DDMA_REQ_CWT					2
#define DDMA_REQ_EAC_AC_RD				3
#define DDMA_REQ_EAC_AC_WR				4
#define DDMA_REQ_EAC_MB_UL_RD			5
#define DDMA_REQ_EAC_MB_UL_WR			6
#define DDMA_REQ_EAC_MD_DL_RD			7
#define DDMA_REQ_EAC_MD_DL_WR			8
#define DDMA_REQ_EAC_BT_UL_RD			9
#define DDMA_REQ_EAC_BT_UL_WR			10
#define DDMA_REQ_EAC_BT_DL_RD			11
#define DDMA_REQ_EAC_BT_DL_WR			12
#define DDMA_REQ_MCBSP1_TX				13
#define DDMA_REQ_MCBSP1_RX				14
#define DDMA_REQ_MCBSP2_TX				15
#define DDMA_REQ_MCBSP2_RX				16
#define DDMA_REQ_UART3_TX				17
#define DDMA_REQ_UART3_RX				18
#define DDMA_REQ_UNCONNECTED_19			19
#define DDMA_REQ_UNCONNECTED_20			20
#define DDMA_REQ_UNCONNECTED_21			21
#define DDMA_REQ_UNCONNECTED_22			22
#define DDMA_REQ_UNCONNECTED_23			23
#define DDMA_REQ_UNCONNECTED_24			24
#define DDMA_REQ_UNCONNECTED_25			25
#define DDMA_REQ_UNCONNECTED_26			26
#define DDMA_REQ_UNCONNECTED_27			27
#define DDMA_REQ_UNCONNECTED_28			28
#define DDMA_REQ_UNCONNECTED_29			29
#define DDMA_REQ_UNCONNECTED_30			30
#define DDMA_REQ_UNCONNECTED_31			31
#define DDMA_REQ_UNCONNECTED_32			32

//------------------------------------------------------------------------------
// CCR register fields

#define DMA_CCR_BUFFERING_DISABLE           (1 << 25)
#define DMA_CCR_SEL_SRC_DST_SYNCH           (1 << 24)
#define DMA_CCR_PREFETCH                    (1 << 23)
#define DMA_CCR_SUPERVISOR                  (1 << 22)
#define DMA_CCR_SECURE                      (1 << 21)
#define DMA_CCR_BS                          (1 << 18)
#define DMA_CCR_TRANSPARENT_COPY_ENABLE     (1 << 17)
#define DMA_CCR_CONST_FILL_ENABLE           (1 << 16)

#define DMA_CCR_DST_AMODE_MASK              (3 << 14)
#define DMA_CCR_DST_AMODE_DOUBLE            (3 << 14)
#define DMA_CCR_DST_AMODE_SINGLE            (2 << 14)
#define DMA_CCR_DST_AMODE_POST_INC          (1 << 14)
#define DMA_CCR_DST_AMODE_CONST             (0 << 14)

#define DMA_CCR_SRC_AMODE_MASK              (3 << 12)
#define DMA_CCR_SRC_AMODE_DOUBLE            (3 << 12)
#define DMA_CCR_SRC_AMODE_SINGLE            (2 << 12)
#define DMA_CCR_SRC_AMODE_POST_INC          (1 << 12)
#define DMA_CCR_SRC_AMODE_CONST             (0 << 12)

#define DMA_CCR_WR_ACTIVE                   (1 << 10)
#define DMA_CCR_RD_ACTIVE                   (1 << 9)
#define DMA_CCR_SUSPEND_SENSITIVE           (1 << 8)
#define DMA_CCR_ENABLE                      (1 << 7)
#define DMA_CCR_PRIO                        (1 << 6)
#define DMA_CCR_FS                          (1 << 5)

#define DMA_CCR_SYNC(req)                   (((req) & 0x1F) | (((DWORD)(req) & 0x60) << 14))

//------------------------------------------------------------------------------
// CICR register fields

#define DMA_CICR_MISALIGNED_ERR_IE          (1 << 11)
#define DMA_CICR_SUPERVISOR_ERR_IE          (1 << 10)
#define DMA_CICR_SECURE_ERR_IE              (1 << 9)
#define DMA_CICR_TRANS_ERR_IE               (1 << 8)
#define DMA_CICR_PKT_IE                     (1 << 7)
#define DMA_CICR_BLOCK_IE                   (1 << 5)
#define DMA_CICR_LAST_IE                    (1 << 4)
#define DMA_CICR_FRAME_IE                   (1 << 3)
#define DMA_CICR_HALF_IE                    (1 << 2)
#define DMA_CICR_DROP_IE                    (1 << 1)

//------------------------------------------------------------------------------
// CSR register fields

#define DMA_CSR_MISALIGNED_ERR              (1 << 11)
#define DMA_CSR_SUPERVISOR_ERR              (1 << 10)
#define DMA_CSR_SECURE_ERR                  (1 << 9)
#define DMA_CSR_TRANS_ERR                   (1 << 8)
#define DMA_CSR_PKT                         (1 << 7)
#define DMA_CSR_sync                        (1 << 6)
#define DMA_CSR_BLOCK                       (1 << 5)
#define DMA_CSR_LAST                        (1 << 4)
#define DMA_CSR_FRAME                       (1 << 3)
#define DMA_CSR_HALF                        (1 << 2)
#define DMA_CSR_DROP                        (1 << 1)

//------------------------------------------------------------------------------
// CSR register fields

#define DMA_CSDP_SRC_ENDIAN_BIG                 0x00200000
#define DMA_CSDP_SRC_ENDIAN_LOCK                0x00100000
#define DMA_CSDP_DST_ENDIAN_BIG                 0x00080000
#define DMA_CSDP_DST_ENDIAN_LOCK                0x00040000
#define DMA_CSDP_WRITE_MODE_MASK                0x00030000
#define DMA_CSDP_WRITE_MODE_NOPOST              0x00000000
#define DMA_CSDP_WRITE_MODE_POSTED              0x00010000
#define DMA_CSDP_WRITE_MODE_POSTED_EXCEPT       0x00020000
#define DMA_CSDP_DST_BURST_MASK                 0x0000C000
#define DMA_CSDP_DST_BURST_NONE                 0x00000000
#define DMA_CSDP_DST_BURST_16BYTES_4x32_2x64    0x00004000
#define DMA_CSDP_DST_BURST_32BYTES_8x32_4x64    0x00008000
#define DMA_CSDP_DST_BURST_64BYTES_16x32_8x64   0x0000C000
#define DMA_CSDP_DST_PACKED                     0x00002000
#define DMA_CSDP_WR_ADDR_TRSLT_MASK             0x00001E00
#define DMA_CSDP_SRC_BURST_MASK                 0x00000180
#define DMA_CSDP_SRC_BURST_NONE                 0x00000000
#define DMA_CSDP_SRC_BURST_16BYTES_4x32_2x64    0x00000080
#define DMA_CSDP_SRC_BURST_32BYTES_8x32_4x64    0x00000100
#define DMA_CSDP_SRC_BURST_64BYTES_16x32_8x64   0x00000180
#define DMA_CSDP_SRC_PACKED                     0x00000040
#define DMA_CSDP_RD_ADDR_TRSLT_MASK             0x0000003C
#define DMA_CSDP_DATATYPE_MASK                  0x00000003
#define DMA_CSDP_DATATYPE_8BIT                  0x00000000
#define DMA_CSDP_DATATYPE_16BIT                 0x00000001
#define DMA_CSDP_DATATYPE_32BIT                 0x00000002


//------------------------------------------------------------------------------
// CLNK_CTRL register fields

#define DMA_CLNK_CTRL_ENABLE_LINK           (1 << 15)

//------------------------------------------------------------------------------

#define DMA_LCD_CSDP_B2_BURST_MASK          (3 << 14)
#define DMA_LCD_CSDP_B2_BURST_4             (2 << 14)
#define DMA_LCD_CSDP_B2_BURST_NONE          (0 << 14)

#define DMA_LCD_CSDP_B2_PACK                (1 << 13)

#define DMA_LCD_CSDP_B2_DATA_TYPE_MASK      (3 << 11)
#define DMA_LCD_CSDP_B2_DATA_TYPE_S32       (2 << 11)
#define DMA_LCD_CSDP_B2_DATA_TYPE_S16       (1 << 11)
#define DMA_LCD_CSDP_B2_DATA_TYPE_S8        (0 << 11)

#define DMA_LCD_CSDP_B1_BURST_MASK          (3 << 7)
#define DMA_LCD_CSDP_B1_BURST_4             (2 << 7)
#define DMA_LCD_CSDP_B1_BURST_NONE          (0 << 7)

#define DMA_LCD_CSDP_B1_PACK                (1 << 6)

#define DMA_LCD_CSDP_B1_DATA_TYPE_MASK      (3 << 0)
#define DMA_LCD_CSDP_B1_DATA_TYPE_S32       (2 << 0)
#define DMA_LCD_CSDP_B1_DATA_TYPE_S16       (1 << 0)
#define DMA_LCD_CSDP_B1_DATA_TYPE_S8        (0 << 0)

//------------------------------------------------------------------------------

#define DMA_LCD_CCR_B2_AMODE_MASK           (3 << 14)
#define DMA_LCD_CCR_B2_AMODE_DOUBLE         (3 << 14)
#define DMA_LCD_CCR_B2_AMODE_SINGLE         (2 << 14)
#define DMA_LCD_CCR_B2_AMODE_INC            (1 << 14)

#define DMA_LCD_CCR_B1_AMODE_MASK           (3 << 12)
#define DMA_LCD_CCR_B1_AMODE_DOUBLE         (3 << 12)
#define DMA_LCD_CCR_B1_AMODE_SINGLE         (2 << 12)
#define DMA_LCD_CCR_B1_AMODE_INC            (1 << 12)

#define DMA_LCD_CCR_END_PROG                (1 << 11)
#define DMA_LCD_CCR_OMAP32                  (1 << 10)
#define DMA_LCD_CCR_REPEAT                  (1 << 9)
#define DMA_LCD_CCR_AUTO_INIT               (1 << 8)
#define DMA_LCD_CCR_EN                      (1 << 7)
#define DMA_LCD_CCR_PRIO                    (1 << 6)
#define DMA_LCD_CCR_SYNC_PR                 (1 << 4)

//------------------------------------------------------------------------------

#define DMA_LCD_CTRL_EXTERNAL_LCD           (1 << 8)

#define DMA_LCD_CTRL_SOURCE_PORT_MASK       (3 << 6)
#define DMA_LCD_CTRL_SOURCE_PORT_SDRAM      (0 << 6)
#define DMA_LCD_CTRL_SOURCE_PORT_OCP_T1     (1 << 6)
#define DMA_LCD_CTRL_SOURCE_PORT_OCP_T2     (2 << 6)

#define DMA_LCD_CTRL_BLOCK_MODE             (1 << 0)

//------------------------------------------------------------------------------

#define DMA_LCD_LCH_CTRL_TYPE_D             (4 << 0)



#endif