📄 omap3_cm.h
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//
// Copyright (c) Special Computing. All rights reserved.
// Copyright (c) Microsoft Corporation. All rights reserved.
// Copyright (c) Texas Instruments Corporation. All rights reserved.
//
//------------------------------------------------------------------------------
//
// Header: omap3_cm.h
//
// This header file is comprised of clock module register details defined as
// structures and macros for configuring and controlling clocks to different
// SoC modules.
//
//------------------------------------------------------------------------------
#ifndef __OMAP3_CM_H
#define __OMAP3_CM_H
#if __cplusplus
extern "C" {
#endif
//------------------------------------------------------------------------------
// Base Address : OMAP3_CM_MPU_REGS_PA
//------------------------------------------------------------------------------
typedef volatile struct {
UINT32 ulRESERVED_0x00; //offset 0x00,
UINT32 ulCLKEN_PLL; //offset 0x04,
UINT32 ulRESERVED_0x08[6]; //offset 0x08,
UINT32 ulIDLEST; //offset 0x20,
UINT32 ulIDLEST_PLL; //offset 0x24,
UINT32 ulRESERVED_0x28[3]; //offset 0x28,
UINT32 ulAUTOIDLE_PLL; //offset 0x34,
UINT32 ulRESERVED_0x38[2]; //offset 0x38,
UINT32 ulCLKSEL1_PLL; //offset 0x40,
UINT32 ulCLKSEL2_PLL; //offset 0x44,
UINT32 ulCLKSTCTRL; //offset 0x48,
UINT32 ulCLKSTST; //offset 0x4C,
}
OMAP3_CM_MPU_REGS;
//------------------------------------------------------------------------------
// Base Address : OMAP3_CM_CORE_REGS_PA
//------------------------------------------------------------------------------
typedef volatile struct {
UINT32 ulFCLKEN1; //offset 0x00,
UINT32 ulRESERVED_0x04; //offset 0x04,
UINT32 ulFCLKEN3; //offset 0x08,
UINT32 ulRESERVED_0x0C; //offset 0x0C,
UINT32 ulICLKEN1; //offset 0x10,
UINT32 ulICLKEN2; //offset 0x14,
UINT32 ulICLKEN3; //offset 0x18,
UINT32 ulRESERVED_0x1C; //offset 0x1C,
UINT32 ulIDLEST1; //offset 0x20,
UINT32 ulIDLEST2; //offset 0x24,
UINT32 ulIDLEST3; //offset 0x28,
UINT32 ulRESERVED_0x2C; //offset 0x2C,
UINT32 ulAUTOIDLE1; //offset 0x30,
UINT32 ulAUTOIDLE2; //offset 0x34,
UINT32 ulAUTOIDLE3; //offset 0x38,
UINT32 ulRESERVED_0x3C; //offset 0x3C,
UINT32 ulCLKSEL; //offset 0x40,
UINT32 ulRESERVED_0x44; //offset 0x44,
UINT32 ulCLKSTCTRL; //offset 0x48,
UINT32 ulCLKSTST; //offset 0x4C,
}
OMAP3_CM_CORE_REGS;
//------------------------------------------------------------------------------
// Base Address : OMAP3_CM_WKUP_REGS_PA
//------------------------------------------------------------------------------
typedef volatile struct {
UINT32 ulFCLKEN; //offset 0x00,
UINT32 ulRESERVED_0x04; //offset 0x04,
UINT32 ulRESERVED_0x08; //offset 0x08,
UINT32 ulRESERVED_0x0C; //offset 0x0C,
UINT32 ulICLKEN; //offset 0x10,
UINT32 ulRESERVED_0x14; //offset 0x14,
UINT32 ulRESERVED_0x18; //offset 0x18,
UINT32 ulRESERVED_0x1C; //offset 0x1C,
UINT32 ulIDLEST; //offset 0x20,
UINT32 ulRESERVED_0x24; //offset 0x24,
UINT32 ulRESERVED_0x28; //offset 0x28,
UINT32 ulRESERVED_0x2C; //offset 0x2C,
UINT32 ulAUTOIDLE; //offset 0x30,
UINT32 ulRESERVED_0x34; //offset 0x34,
UINT32 ulRESERVED_0x38; //offset 0x38,
UINT32 ulRESERVED_0x3C; //offset 0x3C,
UINT32 ulCLKSEL; //offset 0x40,
}
OMAP3_CM_WKUP_REGS;
#define CM_CORE_FCLKEN1_EN_MCBSP1 BIT9
#define CM_CORE_FCLKEN1_EN_MCBSP5 BIT10
#define CM_CORE_FCLKEN1_EN_GPT10 BIT11
#define CM_CORE_FCLKEN1_EN_GPT11 BIT12
#define CM_CORE_FCLKEN1_EN_UART1 BIT13
#define CM_CORE_FCLKEN1_EN_UART2 BIT14
#define CM_CORE_FCLKEN1_EN_I2C1 BIT15
#define CM_CORE_FCLKEN1_EN_I2C2 BIT16
#define CM_CORE_FCLKEN1_EN_I2C3 BIT17
#define CM_CORE_FCLKEN1_EN_MCSPI1 BIT18
#define CM_CORE_FCLKEN1_EN_MCSPI2 BIT19
#define CM_CORE_FCLKEN1_EN_MCSPI3 BIT20
#define CM_CORE_FCLKEN1_EN_MCSPI4 BIT21
#define CM_CORE_FCLKEN1_EN_HDQ BIT22
#define CM_CORE_FCLKEN1_EN_MSPRO BIT23
#define CM_CORE_FCLKEN1_EN_MMC1 BIT24
#define CM_CORE_FCLKEN1_EN_MMC2 BIT25
#define CM_CORE_FCLKEN1_EN_MMC3 BIT30
#define CM_CORE_FCLKEN3_EN_CPEFUSE BIT0
#define CM_CORE_FCLKEN3_EN_TS BIT1
#define CM_CORE_FCLKEN3_EN_USBTLL BIT2
#define CM_CORE_ICLKEN1_EN_SDRC BIT1
#define CM_CORE_ICLKEN1_EN_HSOTGUSB BIT4
#define CM_CORE_ICLKEN1_EN_OMAPCTRL BIT6
#define CM_CORE_ICLKEN1_EN_MAILBOXES BIT7
#define CM_CORE_ICLKEN1_EN_MCBSP1 BIT9
#define CM_CORE_ICLKEN1_EN_MCBSP5 BIT10
#define CM_CORE_ICLKEN1_EN_GPT10 BIT11
#define CM_CORE_ICLKEN1_EN_GPT11 BIT12
#define CM_CORE_ICLKEN1_EN_UART1 BIT13
#define CM_CORE_ICLKEN1_EN_UART2 BIT14
#define CM_CORE_ICLKEN1_EN_I2C1 BIT15
#define CM_CORE_ICLKEN1_EN_I2C2 BIT16
#define CM_CORE_ICLKEN1_EN_I2C3 BIT17
#define CM_CORE_ICLKEN1_EN_MCSPI1 BIT18
#define CM_CORE_ICLKEN1_EN_MCSPI2 BIT19
#define CM_CORE_ICLKEN1_EN_MCSPI3 BIT20
#define CM_CORE_ICLKEN1_EN_MCSPI4 BIT21
#define CM_CORE_ICLKEN1_EN_HDQ BIT22
#define CM_CORE_ICLKEN1_EN_MSPRO BIT23
#define CM_CORE_ICLKEN1_EN_MMC1 BIT24
#define CM_CORE_ICLKEN1_EN_MMC2 BIT25
#define CM_CORE_ICLKEN1_EN_DES2 BIT26
#define CM_CORE_ICLKEN1_EN_SHA12 BIT27
#define CM_CORE_ICLKEN1_EN_AES2 BIT28
#define CM_CORE_ICLKEN1_EN_ICR BIT29
#define CM_CORE_ICLKEN1_EN_MMC3 BIT30
#define CM_CORE_ICLKEN2_EN_DES1 BIT0
#define CM_CORE_ICLKEN2_EN_SHA11 BIT1
#define CM_CORE_ICLKEN2_EN_RNG BIT2
#define CM_CORE_ICLKEN2_EN_AES1 BIT3
#define CM_CORE_ICLKEN2_EN_PKA BIT4
#define CM_CORE_ICLKEN3_EN_USBTLL BIT2
#define CM_WKUP_FCLKEN_EN_GPT1 BIT0
#define CM_WKUP_FCLKEN_EN_GPIO1 BIT3
#define CM_WKUP_FCLKEN_EN_WDT2 BIT5
#define CM_WKUP_FCLKEN_EN_SR1 BIT6
#define CM_WKUP_FCLKEN_EN_SR2 BIT7
#define CM_WKUP_FCLKEN_EN_USIMOPC BIT9
#define CM_WKUP_ICLKEN_EN_GPT1 BIT0
#define CM_WKUP_ICLKEN_EN_GPT12 BIT1
#define CM_WKUP_ICLKEN_EN_32KSYNC BIT2
#define CM_WKUP_ICLKEN_EN_GPIO1 BIT3
#define CM_WKUP_ICLKEN_EN_WDT1 BIT4
#define CM_WKUP_ICLKEN_EN_WDT2 BIT5
#define CM_WKUP_ICLKEN_EN_SR1 BIT6
#define CM_WKUP_ICLKEN_EN_SR2 BIT7
#define CM_WKUP_ICLKEN_EN_USIMOPC BIT9
//------------------------------------------------------------------------------
#if __cplusplus
}
#endif
#endif
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