omap3_timer.h

Windows CE 6.0 BSP for the Beagle Board.

//
// Copyright (c) Special Computing.  All rights reserved. 
// Copyright (c) Microsoft Corporation.  All rights reserved.
// Copyright (c) Texas Instruments Corporation.  All rights reserved. 
//
//------------------------------------------------------------------------------
//
//  Header:  omap3_timer.h
//
//  This header file is comprised of timer module register details defined as 
//  structures and macros for configuring and controlling the general purpose
//  timers.
//
//------------------------------------------------------------------------------
#ifndef __OMAP3_TIMER_H
#define __OMAP3_TIMER_H

#if __cplusplus
extern "C" {
#endif

//------------------------------------------------------------------------------
// Base Address :	OMAP3_GPTIMER1_REGS_PA	 
//					OMAP3_GPTIMER2_REGS_PA	 
//					OMAP3_GPTIMER3_REGS_PA	 
//					OMAP3_GPTIMER4_REGS_PA	 
//					OMAP3_GPTIMER5_REGS_PA	
//					OMAP3_GPTIMER6_REGS_PA	
//					OMAP3_GPTIMER7_REGS_PA	
//					OMAP3_GPTIMER8_REGS_PA	
//					OMAP3_GPTIMER9_REGS_PA	
//					OMAP3_GPTIMER10_REGS_PA
//					OMAP3_GPTIMER11_REGS_PA
//					OMAP3_GPTIMER12_REGS_PA
//
// Note: Not all of the following registers are available to all timers.
//------------------------------------------------------------------------------

typedef volatile struct {
	UINT32 ulTIDR;						// offset 0x00, Identification register
	UINT32 ulRESERVED_0x4;
	UINT32 ulRESERVED_0x8;
	UINT32 ulRESERVED_0xC;
	UINT32 ulTIOCP;						// offset 0x10, L4 I/F config reg
	UINT32 ulTISTAT;   					// offset 0x14, Timer sys status reg
	UINT32 ulTISR;     					// offset 0x18, Timer interrupt stat
	UINT32 ulTIER;     					// offset 0x1C, Timer interrupt enable
	UINT32 ulTWER;     					// offset 0x20, Timer wake-up enable
	UINT32 ulTCLR;     					// offset 0x24, Timer control
	UINT32 ulTCRR;     					// offset 0x28, Timer counter register
	UINT32 ulTLDR;     					// offset 0x2C, Timer load register
	UINT32 ulTTGR;     					// offset 0x30, Timer trigger register
	UINT32 ulTWPS;     					// offset 0x34, Timer write posted stat
	UINT32 ulTMAR;     					// offset 0x38, Timer match value reg
	UINT32 ulTCAR1;    					// offset 0x3C, Timer counter1 capt reg
	UINT32 ulTSICR;    					// offset 0x40, L4 I/F sync ctrl reg
	UINT32 ulTCAR2;    					// offset 0x44, Timer counter2 capt reg
	UINT32 ulTPIR;    					// offset 0x48,
	UINT32 ulTNIR;    					// offset 0x4C,
	UINT32 ulTCVR;    					// offset 0x50,
	UINT32 ulTOCR;    					// offset 0x54,
	UINT32 ulTOWR;    					// offset 0x58,
}
OMAP3_GPTIMER_REGS;



//------------------------------------------------------------------------------
// Base Address : OMAP3_TIMER32K_REGS_PA
//------------------------------------------------------------------------------

typedef volatile struct {
	UINT32 ulRESERVED_0x00;				//offset 0x00,
	UINT32 ulSYSCONFIG;					//offset 0x04,
	UINT32 ulRESERVED_0x08;				//offset 0x08,
	UINT32 ulRESERVED_0x0C;				//offset 0x0C,
	UINT32 ulCR;						//offset 0x10,
}
OMAP3_TIMER32K_REGS;

#define OMAP3_GPTIMER_COUNTS_PER_1MS	(32768/1000)

//------------------------------------------------------------------------------

#define TIOCP_EMUFREE       	(1 << 5)
#define TIOCP_FORCE_IDLE    	(0 << 3)
#define TIOCP_NO_IDLE       	(1 << 3)
#define TIOCP_SMART_IDLE    	(2 << 3)
#define TIOCP_ENAWAKEUP     	(1 << 2)
#define TIOCP_RESET         	(1 << 1)
#define TIOCP_AUTOIDLE      	(1 << 0)

//------------------------------------------------------------------------------

#define TISTAT_RESETDONE		(1 << 0)

//------------------------------------------------------------------------------

#define TIER_CAPTURE        	(1 << 2)
#define TIER_OVERFLOW       	(1 << 1)
#define TIER_MATCH          	(1 << 0)

//------------------------------------------------------------------------------

#define TWER_CAPTURE        	(1 << 2)
#define TWER_OVERFLOW       	(1 << 1)
#define TWER_MATCH          	(1 << 0)

//------------------------------------------------------------------------------

#define TCLR_PT             	(1 << 12)
#define TCLR_TRG_OVERFLOWMATCH  (2 << 10)
#define TCLR_TRG_OVERFLOW   	(1 << 10)
#define TCLR_CE             	(1 << 6)
#define TCLR_PRE            	(1 << 5)
#define TCLR_AR             	(1 << 1)
#define TCLR_ST             	(1 << 0)

//------------------------------------------------------------------------------

#define TWPS_TMAR           	(1 << 4)
#define TWPS_TTGR           	(1 << 3)
#define TWPS_TLDR           	(1 << 2)
#define TWPS_TCRR           	(1 << 1)
#define TWPS_TCLR           	(1 << 0)

//------------------------------------------------------------------------------

#define TSICR_POSTED        	(1 << 2)
#define TSICR_SFT           	(1 << 1)

//------------------------------------------------------------------------------

#define TISR_TCAR           	(1 << 2)
#define TISR_OVERFLOW         	(1 << 1)
#define TISR_MAT            	(1 << 0)

//------------------------------------------------------------------------------

#define TLCR_GPO_CFG        	(1 << 14)
#define TLCR_CAPT_MODE      	(1 << 13)
#define TLCR_PT             	(1 << 12)
#define TLCR_SCPWM          	(1 << 7)
#define TLCR_CE             	(1 << 6)
#define TLCR_PRE            	(1 << 5)
#define TLCR_AR             	(1 << 1)
#define TLCR_ST             	(1 << 0)

#define TLCR_TRG_SHIFT      	(10)
#define TLCR_TCM_SHIFT      	(8)
#define TLCR_PTV_SHIFT      	(2)

//------------------------------------------------------------------------------


#if __cplusplus
}
#endif

#endif