omap3_uart.h

Windows CE 6.0 BSP for the Beagle Board.

#define UART_TCR_RX_FIFO_TRIG_HALT_24     (6 << 0)
#define UART_TCR_RX_FIFO_TRIG_HALT_28     (7 << 0)
#define UART_TCR_RX_FIFO_TRIG_HALT_32     (8 << 0)
#define UART_TCR_RX_FIFO_TRIG_HALT_36     (9 << 0)
#define UART_TCR_RX_FIFO_TRIG_HALT_40    (10 << 0)
#define UART_TCR_RX_FIFO_TRIG_HALT_44    (11 << 0)
#define UART_TCR_RX_FIFO_TRIG_HALT_48    (12 << 0)
#define UART_TCR_RX_FIFO_TRIG_HALT_52    (13 << 0)
#define UART_TCR_RX_FIFO_TRIG_HALT_56    (14 << 0)
#define UART_TCR_RX_FIFO_TRIG_HALT_60    (15 << 0)

#define UART_TLR_RX_FIFO_TRIG_DMA_0       (0 << 4)
#define UART_TLR_RX_FIFO_TRIG_DMA_4       (1 << 4)
#define UART_TLR_RX_FIFO_TRIG_DMA_8       (2 << 4)
#define UART_TLR_RX_FIFO_TRIG_DMA_12      (3 << 4)
#define UART_TLR_RX_FIFO_TRIG_DMA_16      (4 << 4)
#define UART_TLR_RX_FIFO_TRIG_DMA_20      (5 << 4)
#define UART_TLR_RX_FIFO_TRIG_DMA_24      (6 << 4)
#define UART_TLR_RX_FIFO_TRIG_DMA_28      (7 << 4)
#define UART_TLR_RX_FIFO_TRIG_DMA_32      (8 << 4)
#define UART_TLR_RX_FIFO_TRIG_DMA_36      (9 << 4)
#define UART_TLR_RX_FIFO_TRIG_DMA_40     (10 << 4)
#define UART_TLR_RX_FIFO_TRIG_DMA_44     (11 << 4)
#define UART_TLR_RX_FIFO_TRIG_DMA_48     (12 << 4)
#define UART_TLR_RX_FIFO_TRIG_DMA_52     (13 << 4)
#define UART_TLR_RX_FIFO_TRIG_DMA_56     (14 << 4)
#define UART_TLR_RX_FIFO_TRIG_DMA_60     (15 << 4)
#define UART_TLR_TX_FIFO_TRIG_DMA_0       (0 << 0)
#define UART_TLR_TX_FIFO_TRIG_DMA_4       (1 << 0)
#define UART_TLR_TX_FIFO_TRIG_DMA_8       (2 << 0)
#define UART_TLR_TX_FIFO_TRIG_DMA_12      (3 << 0)
#define UART_TLR_TX_FIFO_TRIG_DMA_16      (4 << 0)
#define UART_TLR_TX_FIFO_TRIG_DMA_20      (5 << 0)
#define UART_TLR_TX_FIFO_TRIG_DMA_24      (6 << 0)
#define UART_TLR_TX_FIFO_TRIG_DMA_28      (7 << 0)
#define UART_TLR_TX_FIFO_TRIG_DMA_32      (8 << 0)
#define UART_TLR_TX_FIFO_TRIG_DMA_36      (9 << 0)
#define UART_TLR_TX_FIFO_TRIG_DMA_40     (10 << 0)
#define UART_TLR_TX_FIFO_TRIG_DMA_44     (11 << 0)
#define UART_TLR_TX_FIFO_TRIG_DMA_48     (12 << 0)
#define UART_TLR_TX_FIFO_TRIG_DMA_52     (13 << 0)
#define UART_TLR_TX_FIFO_TRIG_DMA_56     (14 << 0)
#define UART_TLR_TX_FIFO_TRIG_DMA_60     (15 << 0)

#define UART_MSR_NCD                      (1 << 7)
#define UART_MSR_NRI                      (1 << 6)
#define UART_MSR_NDSR                     (1 << 5)
#define UART_MSR_NCTS                     (1 << 4)
#define UART_MSR_DCD                      (1 << 3)
#define UART_MSR_RI                       (1 << 2)
#define UART_MSR_DSR                      (1 << 1)
#define UART_MSR_CTS                      (1 << 0)

#define UART_IER_CST                      (1 << 7)
#define UART_IER_RTS                      (1 << 6)
#define UART_IER_XOFF                     (1 << 5)
#define UART_IER_SLEEP_MODE               (1 << 4)
#define UART_IER_MODEM                    (1 << 3)
#define UART_IER_LINE                     (1 << 2)
#define UART_IER_THR                      (1 << 1)
#define UART_IER_RHR                      (1 << 0)

#define IRDA_IER_EOF_IT                   (1 << 7)
#define IRDA_IER_LINE_STS_IT              (1 << 6)
#define IRDA_IER_TX_STATUS_IT             (1 << 5)
#define IRDA_IER_STS_FIFO_IT              (1 << 4)
#define IRDA_IER_RX_OE_IT                 (1 << 3)
#define IRDA_IER_RX_FIFO_LAST_BYTE_IT     (1 << 2)
#define IRDA_IER_THR_IT                   (1 << 1)
#define IRDA_IER_RHR_IT                   (1 << 0)

#define UART_IIR_MODEM                    (0 << 1)
#define UART_IIR_THR                      (1 << 1)
#define UART_IIR_RHR                      (2 << 1)
#define UART_IIR_LINE                     (3 << 1)
#define UART_IIR_TO                       (6 << 1)
#define UART_IIR_XOFF                     (8 << 1)
#define UART_IIR_HW                      (16 << 1)
#define UART_IIR_IT_PENDING               (1 << 0)

#define IRDA_IIR_EOF_IT                   (1 << 7)
#define IRDA_IIR_LINE_STS_IT              (1 << 6)
#define IRDA_IIR_TX_STATUS_IT             (1 << 5)
#define IRDA_IIR_STS_FIFO_IT              (1 << 4)
#define IRDA_IIR_RX_OE_IT                 (1 << 3)
#define IRDA_IIR_RX_FIFO_LAST_BYTE_IT     (1 << 2)
#define IRDA_IIR_THR_IT                   (1 << 1)
#define IRDA_IIR_RHR_IT                   (1 << 0)

#define UART_FCR_RX_FIFO_LSB_1            (1 << 6)
#define UART_FCR_RX_FIFO_LSB_2            (2 << 6)
#define UART_FCR_RX_FIFO_LSB_3            (3 << 6)
#define UART_FCR_TX_FIFO_LSB_1            (1 << 4)
#define UART_FCR_TX_FIFO_LSB_2            (2 << 4)
#define UART_FCR_TX_FIFO_LSB_3            (3 << 4)

#define UART_FCR_RX_FIFO_TRIG_8           (0 << 6)
#define UART_FCR_RX_FIFO_TRIG_16          (1 << 6)
#define UART_FCR_RX_FIFO_TRIG_56          (2 << 6)
#define UART_FCR_RX_FIFO_TRIG_60          (3 << 6)
#define UART_FCR_TX_FIFO_TRIG_8           (0 << 4)
#define UART_FCR_TX_FIFO_TRIG_16          (1 << 4)
#define UART_FCR_TX_FIFO_TRIG_32          (2 << 4)
#define UART_FCR_TX_FIFO_TRIG_56          (3 << 4)
#define UART_FCR_DMA_MODE                 (1 << 3)
#define UART_FCR_TX_FIFO_CLEAR            (1 << 2)
#define UART_FCR_RX_FIFO_CLEAR            (1 << 1)
#define UART_FCR_FIFO_EN                  (1 << 0)

#define UART_SCR_RX_TRIG_GRANU1           (1 << 7)
#define UART_SCR_TX_TRIG_GRANU1           (1 << 6)
#define UART_SCR_DSR_IT                   (1 << 5)
#define UART_SCR_RX_CTS_DSR_WAKE_UP_ENABLE (1 << 4)
#define UART_SCR_TX_EMPTY_CTL             (1 << 3)
#define UART_SCR_DMA_MODE_2_MODE0         (0 << 1)
#define UART_SCR_DMA_MODE_2_MODE1         (1 << 1)
#define UART_SCR_DMA_MODE_2_MODE2         (2 << 1)
#define UART_SCR_DMA_MODE_2_MODE3         (3 << 1)
#define UART_SCR_DMA_MODE_CTL             (1 << 0)

#define UART_SSR_TX_FIFO_FULL             (1 << 0)

#define UART_SYSC_IDLE_FORCE              (0 << 3)
#define UART_SYSC_IDLE_DISABLED           (1 << 3)
#define UART_SYSC_IDLE_SMART              (2 << 3)
#define UART_SYSC_WAKEUP_ENABLE           (1 << 2)
#define UART_SYSC_RST                     (1 << 1)
#define UART_SYSC_AUTOIDLE                (1 << 0)

#define UART_SYSS_RST_DONE                (1 << 0)

#define UART_MDR1_UART16                  (0 << 0)
#define UART_MDR1_SIR                     (1 << 0)
#define UART_MDR1_UART16AUTO              (2 << 0)
#define UART_MDR1_UART13                  (3 << 0)
#define UART_MDR1_MIR                     (4 << 0)
#define UART_MDR1_FIR                     (5 << 0)
#define UART_MDR1_DISABLE                 (7 << 0)

#define UART_MDR1_FRAME_END_MODE          (1 << 7)
#define UART_MDR1_SIP_MODE                (1 << 6)
#define UART_MDR1_SCT                     (1 << 5)
#define UART_MDR1_SET_TXIR                (1 << 4)
#define UART_MDR1_IR_SLEEP                (1 << 3)

#define UART_MDR2_STS_FIFO_TRIG           (0x6)
#define UART_MDR2_STS_FIFO_TRIG_1_ENTRY   (0 << 1)
#define UART_MDR2_STS_FIFO_TRIG_4_ENTRY   (1 << 1)
#define UART_MDR2_STS_FIFO_TRIG_7_ENTRY   (2 << 1)
#define UART_MDR2_STS_FIFO_TRIG_8_ENTRY   (3 << 1)
#define UART_MDR2_TX_UNDERRUN             (1 << 0)

#define UART_BLR_STS_FIFO_RESET           (1 << 7)

// ACREG register bit masks
#define IRDA_ACREG_EOT_EN                 (1 << 0)   // end of transmission bits
#define IRDA_ACREG_ABORT_EN               (1 << 1)   // frame abort
#define IRDA_ACREG_SCTX_EN                (1 << 2)   // start frame tx
#define IRDA_ACREG_SEND_SIP               (1 << 3)   // Triggers SIP when set to 1
#define IRDA_ACREG_DIS_TX_UNDERRUN        (1 << 4)   // Disable TX Underrun
#define IRDA_ACREG_DIS_IR_RX              (1 << 5)   // Disable RXIR input
#define IRDA_ACREG_SD_MOD                 (1 << 6)   // SD_MODE control
#define IRDA_ACREG_PULSE_TYPE             (1 << 7)   // SIR pulse width 3/16 or 1.6us

#define UART_EFR_AUTO_CTS_EN              (1 << 7)
#define UART_EFR_AUTO_RTS_EN              (1 << 6)
#define UART_EFR_SPECIAL_CHAR_DETECT      (1 << 5)
#define UART_EFR_ENHANCED_EN              (1 << 4)
#define UART_EFR_SW_FLOW_CONTROL_TX_NONE        (0 << 2)
#define UART_EFR_SW_FLOW_CONTROL_TX_XONOFF1     (2 << 2)
#define UART_EFR_SW_FLOW_CONTROL_TX_XONOFF2     (1 << 2)
#define UART_EFR_SW_FLOW_CONTROL_TX_XONOFF12    (3 << 2)
#define UART_EFR_SW_FLOW_CONTROL_RX_NONE        (0 << 0)
#define UART_EFR_SW_FLOW_CONTROL_RX_XONOFF1     (2 << 0)
#define UART_EFR_SW_FLOW_CONTROL_RX_XONOFF2     (1 << 0)
#define UART_EFR_SW_FLOW_CONTROL_RX_XONOFF12    (3 << 0)

#define IRDA_SFLSR_RX_OE_ERROR            (1 << 4)
#define IRDA_SFLSR_FAME_TO_LONG_ERROR     (1 << 3)
#define IRDA_SFLSR_ABORT_DETECT           (1 << 2)
#define IRDA_SFLSR_CRC_ERROR              (1 << 1)

#define IRDA_BOF             0xC0
#define IRDA_EXTRA_BOF       0xC0
#define IRDA_EOF             0xC1
#define IRDA_ESC             0x7D
#define IRDA_ESC_XOR         0x20

typedef enum _IRDA_DECODE_PROCESS_STATE
{
  STATE_READY = 0,
  STATE_BOF,
  STATE_IN_ESC,
  STATE_RX,
  STATE_SHUTDOWN,
  STATE_COMPLETE
}IRDA_DECODE_PROCESS_STATE;

//------------------------------------------------------------------------------

#if __cplusplus
}
#endif

#endif