omap3_uart.h

Windows CE 6.0 BSP for the Beagle Board.

//
// Copyright (c) Special Computing.  All rights reserved. 
// Copyright (c) Microsoft Corporation.  All rights reserved.
// Copyright (c) Texas Instruments.  All rights reserved. 
//
//------------------------------------------------------------------------------
//
//  Header:	omap3_uart.h
//
//  This header file is comprised of UART module register details defined as
//  structures and macros for configuring and controlling UART module
//
//------------------------------------------------------------------------------
#ifndef __OMAP3_UART_H
#define __OMAP3_UART_H

#if __cplusplus
extern "C" {
#endif

//------------------------------------------------------------------------------
// Base Address : OMAP3_UART1_REGS_PA
//				  OMAP3_UART2_REGS_PA
//				  OMAP3_UART3_REGS_PA
//------------------------------------------------------------------------------

typedef volatile struct
{
   union{                           //offset 0x0
      UINT8 DLL; //config mode A&B, read and write
      UINT8 RHR; //operational mode read
      UINT8 THR; //operational mode write
   };
   UINT8 RESERVED_1[3];
   union{                           //offset 0x4
      UINT8 DLH; //config mode A&B, read and write
      UINT8 IER; //operational mode read and write
   };
   UINT8  RESERVED_2[3];
   union{                           //offset 0x8
      UINT8 IIR; //config mode A read, oper mode read
      UINT8 FCR; //config mode A write,oper mode write
      UINT8 EFR; //config mode B read and write
   };
   UINT8  RESERVED_3[3];
   UINT8 LCR;    //offset 0xC
   UINT8  RESERVED_4[3];
   union{                           //offset 0x10
      UINT8 MCR; //config mode A read & write,
                                    //oper mode read & write
      UINT8 XON1_ADDR1; //config mode B read & write
   };
   UINT8  RESERVED_5[3];
   union{                           //offset 0x14
      UINT8 LSR; //config mode A read, oper mode read
      UINT8 XON2_ADDR2;//config mode B read & write
   };
   UINT8  RESERVED_6[3];
   union{                           //offset 0x18
      UINT8 MSR; //config mode A read & oper mode read
      UINT8 TCR; //all modes
      UINT8 XOFF1;//config mode B read & write
   };
   UINT8  RESERVED_7[3];
   union{                           //offset 0x1C
      UINT8 TLR; //both config mode & oper mode
      UINT8 XOFF2;//config mode B read & write
      UINT8 SPR; //config mode A, oper mode read &write
   };
   UINT8  RESERVED_8[3];
   UINT8 MDR1;   //offset 0x20
   UINT8  RESERVED_9[3];
   UINT8 MDR2;   //offset 0x24
   UINT8  RESERVED_10[3];
   union{                            //offset 0x28
      UINT8 SFLSR;//config mode,oper mode read
      UINT8 TXFLL;//config mode,oper mode write
   };
   UINT8  RESERVED_11[3];
   union{                             //offset 0x2C
      UINT8 RESUME;//config mode,oper mode read
      UINT8 TXFLH; //config mode,oper mode write
   };
   UINT8  RESERVED_12[3];
   union{                             //offset 0x30
      UINT8 SFREGL;//config mode,oper mode read
      UINT8 RXFLL; //config mode,oper mode write
   };
   UINT8  RESERVED_13[3];
   union{                             //offset 0x34
      UINT8 SFREGH;//config mode,oper mode read
      UINT8 RXFLH; //config mode,oper mode write
   };
   UINT8  RESERVED_14[3];
   union{                           //offset 0x38
      UINT8 UASR;//config mode read only
      UINT8 BLR; //oper mode
      UINT8  RESERVED_WRITE_0x30;
   };
   UINT8  RESERVED_15[3];
   union{                            //offset 0x3C
      UINT8 ACREG;//oper mode read & write
      UINT8  RESERVED_CONFIG_0x3C;
   };
   UINT8  RESERVED_16[3];
   UINT8 SCR;                       //offset 0x40
   UINT8  RESERVED_17[3];
   union{                           //offset 0x44
      UINT8 SSR; //read only
      UINT8  RESERVED_WRITE_0x44;
   };
   UINT8  RESERVED_18[3];
   union{                           //offset 0x48
      UINT8 EBLR;//oper mode
      UINT8  RESERVED_CONFIG_0x48;
   };
   UINT8  RESERVED_19[7];
   union{                           //offset 0x50
      UINT8 MVR; //read only
      UINT8  RESERVED_WRITE_0x50;
   };
   UINT8  RESERVED_20[3];
   UINT8 SYSC;  //offset 0x54
   UINT8  RESERVED_21[3];
   union{                         //offset 0x58
      UINT8 SYSS;
      UINT8  RESERVED_WRITE_0x58;
   };
   UINT8  RESERVED_22[3];
   UINT8 WER; //offset 0x5C
   UINT8  RESERVED_23[3];
   UINT8 CFPS;//offset 0x60
}
OMAP3_UART_REGS;

#define UART_FIFO_DEPTH						64

#define UART_LCR_MODE_CONFIG_A            0x80
#define UART_LCR_MODE_CONFIG_B            0xBF
#define UART_LCR_MODE_OPERATIONAL         0x00

#define UART_LCR_DLAB                     (1 << 7)
#define UART_LCR_DIV_EN                   (1 << 7)
#define UART_LCR_BREAK_EN                 (1 << 6)
#define UART_LCR_PARITY_TYPE_2            (1 << 5)
#define UART_LCR_PARITY_TYPE_1            (1 << 4)
#define UART_LCR_PARITY_FORCE_0           (3 << 4)
#define UART_LCR_PARITY_FORCE_1           (2 << 4)
#define UART_LCR_PARITY_EVEN              (1 << 4)
#define UART_LCR_PARITY_ODD               (0 << 4)
#define UART_LCR_PARITY_EN                (1 << 3)
#define UART_LCR_NB_STOP                  (1 << 2)
#define UART_LCR_CHAR_LENGTH_8BIT         (3 << 0)
#define UART_LCR_CHAR_LENGTH_7BIT         (2 << 0)
#define UART_LCR_CHAR_LENGTH_6BIT         (1 << 0)
#define UART_LCR_CHAR_LENGTH_5BIT         (0 << 0)

#define UART_LSR_RX_ERROR                 0x1E

#define UART_LSR_RX_FIFO_STS              (1 << 7)
#define UART_LSR_TX_SR_E                  (1 << 6)
#define UART_LSR_TX_FIFO_E                (1 << 5)
#define UART_LSR_RX_BI                    (1 << 4)
#define UART_LSR_RX_FE                    (1 << 3)
#define UART_LSR_RX_PE                    (1 << 2)
#define UART_LSR_RX_OE                    (1 << 1)
#define UART_LSR_RX_FIFO_E                (1 << 0)

#define IRDA_LSR_THR_EMPTY                (1 << 7)
#define IRDA_LSR_STS_FIFO_FULL            (1 << 6)
#define IRDA_LSR_RX_LAST_BYTE             (1 << 5)
#define IRDA_LSR_FRAME_TOO_LONG           (1 << 4)
#define IRDA_LSR_ABORT                    (1 << 3)
#define IRDA_LSR_CRC                      (1 << 2)
#define IRDA_LSR_STS_FIFO_E               (1 << 1)
#define IRDA_LSR_RX_FIFO_E                (1 << 0)

#define UART_MCR_TCR_TLR                  (1 << 6)
#define UART_MCR_XON_EN                   (1 << 5)
#define UART_MCR_LOOPBACK_EN              (1 << 4)
#define UART_MCR_CD_STS_CH                (1 << 3)
#define UART_MCR_RI_STS_CH                (1 << 2)
#define UART_MCR_RTS                      (1 << 1)
#define UART_MCR_DTR                      (1 << 0)

#define UART_TCR_RX_FIFO_TRIG_START_0     (0 << 4)
#define UART_TCR_RX_FIFO_TRIG_START_4     (1 << 4)
#define UART_TCR_RX_FIFO_TRIG_START_8     (2 << 4)
#define UART_TCR_RX_FIFO_TRIG_START_12    (3 << 4)
#define UART_TCR_RX_FIFO_TRIG_START_16    (4 << 4)
#define UART_TCR_RX_FIFO_TRIG_START_20    (5 << 4)
#define UART_TCR_RX_FIFO_TRIG_START_24    (6 << 4)
#define UART_TCR_RX_FIFO_TRIG_START_28    (7 << 4)
#define UART_TCR_RX_FIFO_TRIG_START_32    (8 << 4)
#define UART_TCR_RX_FIFO_TRIG_START_36    (9 << 4)
#define UART_TCR_RX_FIFO_TRIG_START_40   (10 << 4)
#define UART_TCR_RX_FIFO_TRIG_START_44   (11 << 4)
#define UART_TCR_RX_FIFO_TRIG_START_48   (12 << 4)
#define UART_TCR_RX_FIFO_TRIG_START_52   (13 << 4)
#define UART_TCR_RX_FIFO_TRIG_START_56   (14 << 4)
#define UART_TCR_RX_FIFO_TRIG_START_60   (15 << 4)
#define UART_TCR_RX_FIFO_TRIG_HALT_0      (0 << 0)
#define UART_TCR_RX_FIFO_TRIG_HALT_4      (1 << 0)
#define UART_TCR_RX_FIFO_TRIG_HALT_8      (2 << 0)
#define UART_TCR_RX_FIFO_TRIG_HALT_12     (3 << 0)
#define UART_TCR_RX_FIFO_TRIG_HALT_16     (4 << 0)
#define UART_TCR_RX_FIFO_TRIG_HALT_20     (5 << 0)