📄 omap2420_camera.h
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//
// Copyright (c) Microsoft Corporation. All rights reserved.
//
//
// Use of this sample source code is subject to the terms of the Microsoft
// license agreement under which you licensed this sample source code. If
// you did not accept the terms of the license agreement, you are not
// authorized to use this sample source code. For the terms of the license,
// please see the license agreement between you and Microsoft or, if applicable,
// see the LICENSE.RTF on your install media or the root of your tools installation.
// THE SAMPLE SOURCE CODE IS PROVIDED "AS IS", WITH NO WARRANTIES.
//
//------------------------------------------------------------------------------
//
// File: omap2420_cam.h
//
// This header file is comprised of registers of Camera module
//
#ifndef __OMAP2420_CAMERA_H
#define __OMAP2420_CAMERA_H
//-------------sr - to prevent multiple inclusions ------------------------------------------
#ifndef OMAP2420_CAMSUB_REGS_PA
#define OMAP2420_CAMSUB_REGS_PA 0x48052000
#endif
#ifndef OMAP2420_CAMCORE_REGS_PA
#define OMAP2420_CAMCORE_REGS_PA 0x48052400
#endif
#ifndef OMAP2420_CAMDMA_REGS_PA
#define OMAP2420_CAMDMA_REGS_PA 0x48052800
#endif
//
// Camera Subsystem Registers
//
// CameraTop Subsystem Base Address:
// OMAP2420_CAMSUB_REGS_PA (defined as 0x48052000)
typedef volatile struct {
UINT32 ulCAM_REVISION; //offset 0x0, Camera revision ID
UINT32 ulRESERVED_1[3];
UINT32 ulCAM_SYSCONFIG; //offset 0x10, system config
UINT32 ulCAM_SYSSTATUS; //offset 0x14, system status
UINT32 ulCAM_IRQSTATUS; //offset 0x18, IRQ status
UINT32 ulRESERVED_2[9];
UINT32 ulCAM_GPO; //offset 0x40, GP O/P control
UINT32 ulRESERVED_3[3];
UINT32 ulCAM_GPI; //offset 0x50, GP I/P control
}
OMAP2420_CAMSUB_REGS, *pCAMSUBREGS;
#define OMAP2420_CAMSUB_REVISION_MASK 0x000000FF
#define OMAP2420_CAMSUB_SYSCONFIG_AUTOIDLE 0x00000001
#define OMAP2420_CAMSUB_SYSCONFIG_SOFTRESET 0x00000002
#define OMAP2420_CAMSUB_SYSSTATUS_RESETDONE 0x00000001
#define OMAP2420_CAMSUB_IRQSTATUS_DMAIRQ0 0x00000001
#define OMAP2420_CAMSUB_IRQSTATUS_DMAIRQ1 0x00000002
#define OMAP2420_CAMSUB_IRQSTATUS_DMAIRQ2 0x00000004
#define OMAP2420_CAMSUB_IRQSTATUS_MMUIRQ 0x00000008
#define OMAP2420_CAMSUB_IRQSTATUS_CCIRQ 0x00000010
#define OMAP2420_CAMSUB_GPO_CCP_MODE 0x00000001
#define OMAP2420_CAMSUB_GPO_S_P_EN 0x00000002
#define OMAP2420_CAMSUB_GPI_P_CLK 0x00000001
#define OMAP2420_CAMSUB_GPI_P_HS 0x00000002
#define OMAP2420_CAMSUB_GPI_P_VS 0x00000004
#define OMAP2420_CAMSUB_GPI_P_DATA 0x00007FF8
#define OMAP2420_CAMSUB_GPI_S_CLK 0x00010000
#define OMAP2420_CAMSUB_GPI_S_DATA 0x00020000
#define OMAP2420_CAMSUB_GPI_WAIT 0x00100000
#define OMAP2420_CAMSUB_GPI_MSTANDBY 0x00200000
#define OMAP2420_CAMSUB_GPI_DMA_REQ0 0x00800000
#define OMAP2420_CAMSUB_GPI_DMA_REQ1 0x01000000
//
// Camera Core Registers
//
// Camera Core Base Address:
// OMAP2420_CAMCORE_REGS_PA (defined as 0x48052400)
typedef volatile struct {
UINT32 ulCC_REVISION; //offset 0x00, Core revision
UINT32 ulRESERVED_1[3];
UINT32 ulCC_SYSCONFIG; //offset 0x10, system config
UINT32 ulCC_SYSSTATUS; //offset 0x14, system status
UINT32 ulCC_IRQSTATUS; //offset 0x18, IRQ status
UINT32 ulCC_IRQENABLE; //offset 0x1C, IRQ enable
UINT32 ulRESERVED_2[8];
UINT32 ulCC_CTRL; //offset 0x40, core control
UINT32 ulCC_CTRL_DMA; //offset 0x44, dma control
UINT32 ulCC_CTRL_XCLK; //offset 0x48, XCLK control
UINT32 ulCC_FIFODATA; //offset 0x4C, FIFO data
UINT32 ulCC_TEST; //offset 0x50, TEST
UINT32 ulCC_GENPAR; //offset 0x54, generic params
UINT32 ulCC_CCPFSCR; //offset 0x58, fr strt code(CCP mode)
UINT32 ulCC_CCPFECR; //offset 0x5C, fr end code(CCP mode)
UINT32 ulCC_CCPLSCR; //offset 0x60, ln strt code(CCP mode)
UINT32 ulCC_CCPLECR; //offset 0x64, ln end code(CCP mode)
UINT32 ulCC_CCPDFR; //offset 0x68, sets data format, ECV state mac ctrl
}
OMAP2420_CAMCORE_REGS, *pCAMCOREREGS;
#define OMAP2420_CAMCORE_REVISION_MASK 0x000000FF
#define OMAP2420_CAMCORE_SYSCONF_AUTOIDLE 0x00000001
#define OMAP2420_CAMCORE_SYSCONF_SOFTRESET 0x00000002
#define OMAP2420_CAMCORE_SYSCONF_SIDELMODE_MASK 0x00000018
#define OMAP2420_CAMCORE_SYSSTATUS_RESETDONE 0x00000001
#define OMAP2420_CAMCORE_IRQSTATUS_FIFO_UF_IRQ 0x00000001
#define OMAP2420_CAMCORE_IRQSTATUS_FIFO_OF_IRQ 0x00000002
#define OMAP2420_CAMCORE_IRQSTATUS_FIFO_THR_IRQ 0x00000004
#define OMAP2420_CAMCORE_IRQSTATUS_FIFO_FULL_IRQ 0x00000008
#define OMAP2420_CAMCORE_IRQSTATUS_FIFO_NOEMPTY_IRQ 0x00000010
#define OMAP2420_CAMCORE_IRQSTATUS_SSC_ERR_IRQ 0x00000100
#define OMAP2420_CAMCORE_IRQSTATUS_FSC_ERR_IRQ 0x00000200
#define OMAP2420_CAMCORE_IRQSTATUS_FW_ERR_IRQ 0x00000400
#define OMAP2420_CAMCORE_IRQSTATUS_FSP_ERR_IRQ 0x00000800
#define OMAP2420_CAMCORE_IRQSTATUS_FE_IRQ 0x00010000
#define OMAP2420_CAMCORE_IRQSTATUS_LS_IRQ 0x00020000
#define OMAP2420_CAMCORE_IRQSTATUS_LE_IRQ 0x00040000
#define OMAP2420_CAMCORE_IRQSTATUS_FS_IRQ 0x00080000
#define OMAP2420_CAMCORE_IRQSTATUS_ALL \
(OMAP2420_CAMCORE_IRQSTATUS_FIFO_UF_IRQ | \
OMAP2420_CAMCORE_IRQSTATUS_FIFO_OF_IRQ | \
OMAP2420_CAMCORE_IRQSTATUS_FIFO_THR_IRQ | \
OMAP2420_CAMCORE_IRQSTATUS_FIFO_FULL_IRQ | \
OMAP2420_CAMCORE_IRQSTATUS_FIFO_NOEMPTY_IRQ | \
OMAP2420_CAMCORE_IRQSTATUS_SSC_ERR_IRQ | \
OMAP2420_CAMCORE_IRQSTATUS_FSC_ERR_IRQ | \
OMAP2420_CAMCORE_IRQSTATUS_FW_ERR_IRQ | \
OMAP2420_CAMCORE_IRQSTATUS_FSP_ERR_IRQ | \
OMAP2420_CAMCORE_IRQSTATUS_FE_IRQ | \
OMAP2420_CAMCORE_IRQSTATUS_LS_IRQ | \
OMAP2420_CAMCORE_IRQSTATUS_LE_IRQ | \
OMAP2420_CAMCORE_IRQSTATUS_FS_IRQ)
#define OMAP2420_CAMCORE_IRQENABLE_FIFO_UF_IRQ_EN 0x00000001
#define OMAP2420_CAMCORE_IRQENABLE_FIFO_OF_IRQ_EN 0x00000002
#define OMAP2420_CAMCORE_IRQENABLE_FIFO_THR_IRQ_EN 0x00000004
#define OMAP2420_CAMCORE_IRQENABLE_FIFO_FULL_IRQ_EN 0x00000008
#define OMAP2420_CAMCORE_IRQENABLE_FIFO_NOEMPTY_IRQ_EN 0x00000010
#define OMAP2420_CAMCORE_IRQENABLE_SSC_ERR_IRQ_EN 0x00000100
#define OMAP2420_CAMCORE_IRQENABLE_FSC_ERR_IRQ_EN 0x00000200
#define OMAP2420_CAMCORE_IRQENABLE_FW_ERR_IRQ_EN 0x00000400
#define OMAP2420_CAMCORE_IRQENABLE_FSP_ERR_IRQ_EN 0x00000800
#define OMAP2420_CAMCORE_IRQENABLE_FE_IRQ_EN 0x00010000
#define OMAP2420_CAMCORE_IRQENABLE_LS_IRQ_EN 0x00020000
#define OMAP2420_CAMCORE_IRQENABLE_LE_IRQ_EN 0x00040000
#define OMAP2420_CAMCORE_IRQENABLE_FS_IRQ_EN 0x00080000
#define OMAP2420_CAMCORE_IRQENABLE_ALL \
(OMAP2420_CAMCORE_IRQENABLE_FIFO_UF_IRQ_EN | \
OMAP2420_CAMCORE_IRQENABLE_FIFO_OF_IRQ_EN | \
OMAP2420_CAMCORE_IRQENABLE_FIFO_THR_IRQ_EN | \
OMAP2420_CAMCORE_IRQENABLE_FIFO_FULL_IRQ_EN | \
OMAP2420_CAMCORE_IRQENABLE_FIFO_NOEMPTY_IRQ_EN | \
OMAP2420_CAMCORE_IRQENABLE_SSC_ERR_IRQ_EN | \
OMAP2420_CAMCORE_IRQENABLE_FSC_ERR_IRQ_EN | \
OMAP2420_CAMCORE_IRQENABLE_FW_ERR_IRQ_EN | \
OMAP2420_CAMCORE_IRQENABLE_FSP_ERR_IRQ_EN | \
OMAP2420_CAMCORE_IRQENABLE_FE_IRQ_EN | \
OMAP2420_CAMCORE_IRQENABLE_LS_IRQ_EN | \
OMAP2420_CAMCORE_IRQENABLE_LE_IRQ_EN | \
OMAP2420_CAMCORE_IRQENABLE_FS_IRQ_EN)
#define OMAP2420_CAMCORE_CTRL_CCP_MODE 0x00000001
#define OMAP2420_CAMCORE_CTRL_PAR_MODE_MASK 0x0000000E
#define OMAP2420_CAMCORE_CTRL_PAR_MODE_8_NOBT 0x00000000
#define OMAP2420_CAMCORE_CTRL_PAR_MODE_10_NOBT 0x00000002
#define OMAP2420_CAMCORE_CTRL_PAR_MODE_12_NOBT 0x00000004
#define OMAP2420_CAMCORE_CTRL_PAR_MODE_8_BT 0x00000008
#define OMAP2420_CAMCORE_CTRL_PAR_MODE_10_BT 0x0000000A
#define OMAP2420_CAMCORE_CTRL_PAR_MODE_12_BT 0x0000000E
#define OMAP2420_CAMCORE_CTRL_NOBT_VS_POL 0x00000100
#define OMAP2420_CAMCORE_CTRL_NOBT_HS_POL 0x00000200
#define OMAP2420_CAMCORE_CTRL_PAR_CLK_POL 0x00000400
#define OMAP2420_CAMCORE_CTRL_PAR_ORDERCAM 0x00000800
#define OMAP2420_CAMCORE_CTRL_BT_CORRECT 0x00001000
#define OMAP2420_CAMCORE_CTRL_NOBT_SYNCHRO 0x00002000
#define OMAP2420_CAMCORE_CTRL_CC_EN 0x00010000
#define OMAP2420_CAMCORE_CTRL_CC_FRAME_TRIG 0x00020000
#define OMAP2420_CAMCORE_CTRL_CC_RST 0x00040000
#define OMAP2420_CAMCORE_CTRL_DMA_FIFO_THRESHOLD_MASK 0x0000007F
#define OMAP2420_CAMCORE_CTRL_DMA_FIFO_THRESHOLD_MAX 0x0000007F
#define OMAP2420_CAMCORE_CTRL_DMA_FIFO_THRESHOLD_HALF 0x0000003F
#define OMAP2420_CAMCORE_CTRL_DMA_FIFO_THRESHOLD_QUART 0x0000001F
#define OMAP2420_CAMCORE_CTRL_DMA_DMA_EN 0x00000100
#define OMAP2420_CAMCORE_CTRL_DMA_DMA1_DISABLE 0x00000200
#define OMAP2420_CAMCORE_CTRL_XCLK_DIV_MASK 0x0000001F
#define OMAP2420_CAMCORE_TEST_FIFO_LEVEL_PEAK_MASK 0x000000FF
#define OMAP2420_CAMCORE_TEST_FIFO_LEVEL_MASK 0x0000FF00
#define OMAP2420_CAMCORE_TEST_FIFO_WR_POINTER 0x00FF0000
#define OMAP2420_CAMCORE_TEST_FIFO_RD_POINTER 0xFF000000
#define OMAP2420_CAMCORE_GENPAR_FIFO_DEPTH_MASK 0x00000007
// this register affects ccp mode (serial as opposed to parallel) only
#define OMAP2420_CAMCORE_CCPDFR_ALPHA_MASK 0x0000FF00
#define OMAP2420_CAMCORE_CCPDFR_DATAFORMAT_SELECT_MASK 0x0000000F
#define OMAP2420_CAMCORE_CCPDFG_DATAFORMAT_YUV422BE 0x00000000
#define OMAP2420_CAMCORE_CCPDFG_DATAFORMAT_YUV422 0x00000001
#define OMAP2420_CAMCORE_CCPDFG_DATAFORMAT_YUV420 0x00000002
#define OMAP2420_CAMCORE_CCPDFG_DATAFORMAT_RGB444 0x00000004
#define OMAP2420_CAMCORE_CCPDFG_DATAFORMAT_RGB565 0x00000005
#define OMAP2420_CAMCORE_CCPDFG_DATAFORMAT_RGB888_NDE 0x00000006
#define OMAP2420_CAMCORE_CCPDFG_DATAFORMAT_RGB888_DE 0x00000007
#define OMAP2420_CAMCORE_CCPDFG_DATAFORMAT_RAW8_NDE 0x00000008
#define OMAP2420_CAMCORE_CCPDFG_DATAFORMAT_RAW8_DE 0x00000009
#define OMAP2420_CAMCORE_CCPDFG_DATAFORMAT_RAW10_NDE 0x0000000A
#define OMAP2420_CAMCORE_CCPDFG_DATAFORMAT_RAW10_DE 0x0000000B
#define OMAP2420_CAMCORE_CCPDFG_DATAFORMAT_RAW12_NDE 0x0000000C
#define OMAP2420_CAMCORE_CCPDFG_DATAFORMAT_RAW12_DE 0x0000000D
#define OMAP2420_CAMCORE_CCPDFG_DATAFORMAT_JPEG8_FSP 0x0000000E
#define OMAP2420_CAMCORE_CCPDFG_DATAFORMAT_JPEG8 0x0000000F
#endif // __OMAP2420_CAMERA_H
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