power.c

Windows CE 6.0 BSP for the Beagle Board.

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this sample source code is subject to the terms of the Microsoft
// license agreement under which you licensed this sample source code. If
// you did not accept the terms of the license agreement, you are not
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// please see the license agreement between you and Microsoft or, if applicable,
// see the LICENSE.RTF on your install media or the root of your tools installation.
// THE SAMPLE SOURCE CODE IS PROVIDED "AS IS", WITH NO WARRANTIES.
//
/* ***********************************************************
* THIS PROGRAM IS PROVIDED "AS IS". TI MAKES NO WARRANTIES OR REPRESENTATIONS, EITHER EXPRESS, IMPLIED OR STATUTORY, 
* INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR
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* POSSESSION, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS WITH REGARD TO THE PROGRAM OR 
* YOUR USE OF THE PROGRAM.
*
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* OF THIS AGREEMENT, THE PROGRAM, OR YOUR USE OF THE PROGRAM.  EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF 
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*
* Unless otherwise stated, the Program written and copyrighted by Texas Instruments is distributed as "freeware".  You may, 
* only under TI's copyright in the Program, use and modify the Program without any charge or restriction.  You may 
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*
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//
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
//  File:  power.c
//
#include <windows.h>
#include <ceddk.h>
#include <nkintr.h>
#include <oal.h>
#include <omap2420.h>
#include <bsp.h>

//Assembly routines for context save/restore
VOID OALCPUIdle();
VOID OALCPUIdle_sz();


//Map Public region of SRAM for sleep routines
//Must use cached address range or an exception is thrown
#define OMAP2420_SRAM_API_SUSPEND (OALPAtoCA(0x4020F800))
//#define OMAP2420_SRAM_API_SUSPEND (OALPAtoCA(0xA0100000))

enum
{
    ulINTC_MIR0 = 0,
    ulINTC_MIR1,
    ulINTC_MIR2,
    ulCM_FCLKEN_WKUP,
    ulCM_ICLKEN_WKUP,
    ulGPIO_DATAOUT,
    ulGPIO1_OE,
    ulPADCONF_UART1_RX,
    ulGPIO3_OE,
    ulPADCONF_SPI1_NCS2,
    ulPM_WKEN_WKUP,
    ulGPIO_FALLINGDETECT,
    ulGPIO_SYSCONFIG,
    ulGPIO_WAKEUPENABLE,
    ulGPIO_DEBOUNCINGTIME,
    ulGPIO_DEBOUNCENABLE,
    ulPM_WKEN1_CORE,
    ulPM_WKEN2_CORE,
    ulCM_AUTOIDLE_PLL,
    ulPRCM_CLKSRC_CTRL,
    ulPRCM_CLKSSETUP,
    ulPM_PWSTCTRL_CORE,
    ulPM_WKDEP_MPU,
    ulPM_WKDEP_DSP,
    ulPM_WKDEP_GFX,
    ulGPIO_IRQENABLE1,
    ulPM_PWSTCTRL_MPU,
    ulPM_PWSTCTRL_DSP,
    ulPM_PWSTCTRL_GFX,
    ulSDRC_POWER,
    ulSMS_SYSCONFIG,
    ulSDRC_SYSCONFIG,
    ulGPMC_SYSCONFIG,
    ulCM_CLKSTCTRL_MPU,
    ulCM_CLKSTCTRL_DSP,
    ulCM_CLKSTCTRL_GFX,
    ulCM_CLKSTCTRL_CORE,
    ulCM_AUTOIDLE_DSP,
    ulCM_AUTOIDLE1_CORE,
    ulCM_AUTOIDLE2_CORE,
    ulCM_AUTOIDLE3_CORE,
    ulCM_AUTOIDLE4_CORE,
    ulCM_AUTOIDLE_WKUP,
    ulCM_FCLKEN1_CORE,
    ulCM_FCLKEN2_CORE,

    MAX_REGISTER_CONTEXT
};
UINT32 ulaRegisterContext[MAX_REGISTER_CONTEXT];


//------------------------------------------------------------------------------
//
//  Function:  OEMPowerOff
//
//  Called when the system is to transition to it's lowest power mode (off)
//
VOID OEMPowerOff()
{
//    void (*suspend_func_ptr)();
//    int suspend_func_size;
//    OAL_KITL_ARGS *pArgs;
//    void *pIDCODE_reg;
//    //Declare all register pointers
//    static CPLD_REGS *pCpldRegs;
//    static OMAP2420_MPUINTC_REGS *pIntcRegs;
//    static OMAP2420_GPIO_REGS *pGPIO1Regs;
//    static OMAP2420_GPIO_REGS *pGPIO2Regs;
//    static OMAP2420_GPIO_REGS *pGPIO3Regs;
//    static OMAP2420_GPIO_REGS *pGPIO4Regs;
//    static OMAP2420_PRCM_REGS *pPRCMReg;
//    static OMAP2420_CONTROL_PADCONF_REGS *pPadConfRegs;
//    static OMAP2420_SMS_REGS *pSMSRegs;
//    static OMAP2420_SDRC_REGS *pSDRCRegs;
//    static OMAP2420_GPMC_REGS *pGPMCRegs;
//    static OMAP2420_SYSC1_REGS *pSYSC1Regs;
//    UINT32 new_value = 0x00000000;
//    
//    //Initialize all pointers
//    pCpldRegs    = (CPLD_REGS *) OALPAtoUA(BSP_CPLD_REGS_PA);
//    pIntcRegs    = (OMAP2420_MPUINTC_REGS *) OALPAtoUA(OMAP3_INTC_MPU_REGS_PA);
//    pGPIO1Regs   = (OMAP2420_GPIO_REGS *) OALPAtoUA(OMAP2420_GPIO1_REGS_PA);
//    pGPIO2Regs   = (OMAP2420_GPIO_REGS *) OALPAtoUA(OMAP2420_GPIO2_REGS_PA);
//    pGPIO3Regs   = (OMAP2420_GPIO_REGS *) OALPAtoUA(OMAP2420_GPIO3_REGS_PA);
//    pGPIO4Regs   = (OMAP2420_GPIO_REGS *) OALPAtoUA(OMAP2420_GPIO4_REGS_PA);
//    pPRCMReg     = (OMAP2420_PRCM_REGS *) OALPAtoUA(OMAP2420_PRCM_REGS_PA);
//    pPadConfRegs = (OMAP2420_CONTROL_PADCONF_REGS *) OALPAtoUA(OMAP3_SCM_REGS_PA+0x30);
//    pSMSRegs     = (OMAP2420_SMS_REGS *) OALPAtoUA(OMAP2420_SMS_REGS_PA);
//    pSDRCRegs    = (OMAP2420_SDRC_REGS *) OALPAtoUA(OMAP2420_SDRC_REGS_PA);
//    pGPMCRegs    = (OMAP2420_GPMC_REGS *) OALPAtoUA(OMAP2420_GPMC_REGS_PA);
//    pSYSC1Regs   = (OMAP2420_SYSC1_REGS *) OALPAtoUA(OMAP3_SCM_REGS_PA);
//
//    //Debug Start
//    //OUTREG16(&pCpldRegs->LED, 1);
    OALMSG(1, (L"+OEMPowerOff\r\n"));
//    g_oalWakeSource = SYSWAKE_UNKNOWN;
//
//    //The IDCODE value is 0x0B5D902F for OMAP242x ES1.0.
//    //The IDCODE value is 0x1B5D902F for OMAP242x ES2.0.
//    //The IDCODE value is 0x2B5D902F for OMAP242x ES2.05.
//    //The IDCODE value is 0x3B5D902F for OMAP242x ES2.1 *** Tested PM on this ***
//    //The IDCODE value is 0x4B5D902F for OMAP242x ES2.1.1.
//    pIDCODE_reg = OALPAtoUA(0x48014204);
//    OALMSG(1, (L"OEMPowerOff: IDCODE_reg (%x)\r\n", *(int*)pIDCODE_reg));
//    
//    // Make sure that KITL is powered off
//    pArgs = (OAL_KITL_ARGS*)OALArgsQuery(OAL_ARGS_QUERY_KITL);
//    if ((pArgs->flags & OAL_KITL_FLAGS_ENABLED) != 0)
//    {
//        OALKitlPowerOff();
//        OALMSG(1, (L"OEMPowerOff: KITL Disabled\r\n"));
//    }
//
//    //Backup all used registers
//    ulaRegisterContext[ulINTC_MIR0] = pIntcRegs->ulINTC_MIR0; //restored
//    ulaRegisterContext[ulINTC_MIR1] = pIntcRegs->ulINTC_MIR1; //restored
//    ulaRegisterContext[ulINTC_MIR2] = pIntcRegs->ulINTC_MIR2; //restored
//    ulaRegisterContext[ulCM_FCLKEN_WKUP] = pPRCMReg->ulCM_FCLKEN_WKUP; //restored
//    ulaRegisterContext[ulCM_ICLKEN_WKUP] = pPRCMReg->ulCM_ICLKEN_WKUP; //restored
//    ulaRegisterContext[ulGPIO_DATAOUT] = pGPIO1Regs->ulGPIO_DATAOUT; //restored
//    ulaRegisterContext[ulGPIO1_OE] = pGPIO1Regs->ulGPIO_OE; //restored
//    ulaRegisterContext[ulPADCONF_UART1_RX] = pPadConfRegs->ulPADCONF_UART1_RX; //restored
//    ulaRegisterContext[ulGPIO3_OE] = pGPIO3Regs->ulGPIO_OE; //restored
//    ulaRegisterContext[ulPADCONF_SPI1_NCS2] = pPadConfRegs->ulPADCONF_SPI1_NCS2; //restored
//    ulaRegisterContext[ulPM_WKEN_WKUP] = pPRCMReg->ulPM_WKEN_WKUP; //restored
//    ulaRegisterContext[ulGPIO_FALLINGDETECT] = pGPIO3Regs->ulGPIO_FALLINGDETECT; //restored
//    ulaRegisterContext[ulGPIO_SYSCONFIG] = pGPIO3Regs->ulGPIO_SYSCONFIG; //restored
//    ulaRegisterContext[ulGPIO_WAKEUPENABLE] = pGPIO3Regs->ulGPIO_WAKEUPENABLE; //restored
//    ulaRegisterContext[ulGPIO_DEBOUNCINGTIME] = pGPIO3Regs->ulGPIO_DEBOUNCINGTIME; //restored
//    ulaRegisterContext[ulGPIO_DEBOUNCENABLE] = pGPIO3Regs->ulGPIO_DEBOUNCENABLE; //restored
//    ulaRegisterContext[ulPM_WKEN1_CORE] = pPRCMReg->ulPM_WKEN1_CORE; //restored
//    ulaRegisterContext[ulPM_WKEN2_CORE] = pPRCMReg->ulPM_WKEN2_CORE; //restored
//    ulaRegisterContext[ulCM_AUTOIDLE_PLL] = pPRCMReg->ulCM_AUTOIDLE_PLL; //restored
//    ulaRegisterContext[ulPRCM_CLKSRC_CTRL] = pPRCMReg->ulPRCM_CLKSRC_CTRL; //restored
//    ulaRegisterContext[ulPRCM_CLKSSETUP] = pPRCMReg->ulPRCM_CLKSSETUP; //restored
//    ulaRegisterContext[ulPM_PWSTCTRL_CORE] = pPRCMReg->ulPM_PWSTCTRL_CORE; //restored
//    ulaRegisterContext[ulPM_WKDEP_MPU] = pPRCMReg->ulPM_WKDEP_MPU; //restored
//    ulaRegisterContext[ulPM_WKDEP_DSP] = pPRCMReg->ulPM_WKDEP_DSP; //restored
//    ulaRegisterContext[ulPM_WKDEP_GFX] = pPRCMReg->ulPM_WKDEP_GFX; //restored
//    ulaRegisterContext[ulGPIO_IRQENABLE1] = pGPIO3Regs->ulGPIO_IRQENABLE1; //restored
//    ulaRegisterContext[ulPM_PWSTCTRL_MPU] = pPRCMReg->ulPM_PWSTCTRL_MPU; //restored
//    ulaRegisterContext[ulPM_PWSTCTRL_DSP] = pPRCMReg->ulPM_PWSTCTRL_DSP; //restored
//    ulaRegisterContext[ulPM_PWSTCTRL_GFX] = pPRCMReg->ulPM_PWSTCTRL_GFX; //restored
//    ulaRegisterContext[ulSDRC_POWER] = pSDRCRegs->ulSDRC_POWER;         //restored
//    ulaRegisterContext[ulSMS_SYSCONFIG] = pSMSRegs->ulSMS_SYSCONFIG;    //restored
//    ulaRegisterContext[ulSDRC_SYSCONFIG] = pSDRCRegs->ulSDRC_SYSCONFIG; //restored
//    ulaRegisterContext[ulGPMC_SYSCONFIG] = pGPMCRegs->ulGPMC_SYSCONFIG; //restored
//    ulaRegisterContext[ulCM_CLKSTCTRL_MPU] = pPRCMReg->ulCM_CLKSTCTRL_MPU; //restored
//    ulaRegisterContext[ulCM_CLKSTCTRL_DSP] = pPRCMReg->ulCM_CLKSTCTRL_DSP; //restored
//    ulaRegisterContext[ulCM_CLKSTCTRL_GFX] = pPRCMReg->ulCM_CLKSTCTRL_GFX;  //restored
//    ulaRegisterContext[ulCM_CLKSTCTRL_CORE] = pPRCMReg->ulCM_CLKSTCTRL_CORE; //restored
//    ulaRegisterContext[ulCM_AUTOIDLE_DSP] = pPRCMReg->ulCM_AUTOIDLE_DSP;     //restored
//    ulaRegisterContext[ulCM_AUTOIDLE1_CORE] = pPRCMReg->ulCM_AUTOIDLE1_CORE; //restored
//    ulaRegisterContext[ulCM_AUTOIDLE2_CORE] = pPRCMReg->ulCM_AUTOIDLE2_CORE; //restored
//    ulaRegisterContext[ulCM_AUTOIDLE3_CORE] = pPRCMReg->ulCM_AUTOIDLE3_CORE; //restored
//    ulaRegisterContext[ulCM_AUTOIDLE4_CORE] = pPRCMReg->ulCM_AUTOIDLE4_CORE; //restored
//    ulaRegisterContext[ulCM_AUTOIDLE_WKUP] = pPRCMReg->ulCM_AUTOIDLE_WKUP; //restored
//    ulaRegisterContext[ulCM_FCLKEN1_CORE] = pPRCMReg->ulCM_FCLKEN1_CORE; //restored
//    ulaRegisterContext[ulCM_FCLKEN2_CORE] = pPRCMReg->ulCM_FCLKEN2_CORE; //restored
//
//
//    //Mask all interrupts
//    pIntcRegs->ulINTC_MIR_SET0 = OMAP2420_MPUINTC_MASKALL;
//    pIntcRegs->ulINTC_MIR_SET1 = OMAP2420_MPUINTC_MASKALL;
//    pIntcRegs->ulINTC_MIR_SET2 = OMAP2420_MPUINTC_MASKALL;
//    //Clear isr
//    pIntcRegs->ulINTC_ISR_CLEAR0 = OMAP2420_MPUINTC_MASKALL;
//    pIntcRegs->ulINTC_ISR_CLEAR1 = OMAP2420_MPUINTC_MASKALL;
//    pIntcRegs->ulINTC_ISR_CLEAR2 = OMAP2420_MPUINTC_MASKALL;
//    //Clear current pending isr
//    pIntcRegs->ulINTC_CONTROL = 0x3;
//
//    //functional_clock_control(PRCM_GPIOS, PRCM_ENABLE);
//   	pPRCMReg->ulCM_FCLKEN_WKUP |= PRCM_FCLKEN_WKUP_EN_GPIOS;
//    //interface_clock_control(PRCM_GPIOS, PRCM_ENABLE);
//	pPRCMReg->ulCM_ICLKEN_WKUP |= PRCM_ICLKEN_WKUP_EN_GPIOS;
//
//    //This sets GPIO 12 to drive low
//    pGPIO1Regs->ulGPIO_DATAOUT &= 0xFFFFEFFF; 
//
//    //This sets GPIO 12 as an output
//    pGPIO1Regs->ulGPIO_OE &= 0xFFFFEFFF; 
//
//    //Set up GPIO 12 pin mux
//    //first clear bits for pin P21
//    pPadConfRegs->ulPADCONF_UART1_RX &= 0xFF00FFFF;
//
//    //now set appropriate bits for P21 mode 3, pulldown enabled   
//    pPadConfRegs->ulPADCONF_UART1_RX |= 0x000B0000; 
//
//    //Set GPIO 88 as an input.
//    pGPIO3Regs->ulGPIO_OE |= 0x01000000;
//
//    //GPIO 88 pin mux.
//    //first clear bits for pin T19
//    pPadConfRegs->ulPADCONF_SPI1_NCS2 &= 0xFF00FFFF;
//
//    //now set appropriate bits for T19 mode 3, pullup/pulldown disabled