📄 intr.c
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OALMSG(OAL_INTR, (L"OALIntrEnableIrqs(Irq GPIO5 %d)\r\n", irq - IRQ_GPIO_128));
OUTREG32(&g_pIntcRegs->ulINTC_MIR_CLEAR1, 1<<(IRQ_GPIO5_MPU-32));
OUTREG32(&g_pGPIORegs[4]->ulGPIO_IRQSTATUS1, 1<<(irq - IRQ_GPIO_128)); // clear IRQ
SETREG32(&g_pGPIORegs[4]->ulGPIO_IRQENABLE1, 1<<(irq - IRQ_GPIO_128)); // unmask IRQ
} else if (irq < IRQ_GPIO_192) {
OALMSG(OAL_INTR, (L"OALIntrEnableIrqs(Irq GPIO6 %d)\r\n", irq - IRQ_GPIO_160));
OUTREG32(&g_pIntcRegs->ulINTC_MIR_CLEAR1, 1<<(IRQ_GPIO6_MPU-32));
OUTREG32(&g_pGPIORegs[5]->ulGPIO_IRQSTATUS1, 1<<(irq - IRQ_GPIO_160)); // clear IRQ
SETREG32(&g_pGPIORegs[5]->ulGPIO_IRQENABLE1, 1<<(irq - IRQ_GPIO_160)); // unmask IRQ
} else if (irq != OAL_INTR_IRQ_UNDEFINED) {
rc = FALSE;
}
}
OALMSG(OAL_INTR&&OAL_VERBOSE, (L"-OALIntrEnableIrqs(rc = %d)\r\n", rc));
return rc;
}
//------------------------------------------------------------------------------
//
// Function: OALIntrDisableIrqs
//
VOID OALIntrDisableIrqs(UINT32 count, const UINT32 *pIrqs)
{
UINT32 irq, i;
OALMSG(OAL_INTR&&OAL_FUNC, (
L"+OALIntrDisableIrqs(%d, 0x%08x)\r\n", count, pIrqs
));
for (i = 0; i < count; i++) {
irq = pIrqs[i];
if (irq < 32) {
OUTREG32(&g_pIntcRegs->ulINTC_MIR_SET0, 1 << irq);
} else if (irq < 64) {
OUTREG32(&g_pIntcRegs->ulINTC_MIR_SET1, 1 << (irq - 32));
} else if (irq < 96) {
OUTREG32(&g_pIntcRegs->ulINTC_MIR_SET2, 1 << (irq - 64));
} else if (irq <= IRQ_MENELAUS_PSHBTN) {
OALMSG(OAL_INTR, (L"OALIntrDisableIrqs(Irq MENELAUS %d)\r\n", irq - IRQ_MENELAUS_CD1));
OUTREG32(&g_pIntcRegs->ulINTC_MIR_SET0, 1 << IRQ_SYS_NIRQ);
} else if (irq < IRQ_GPIO_32) {
OALMSG(OAL_INTR, (
L"OALIntrDisableIrqs(Irq GPIO1 %d)\r\n", irq - IRQ_GPIO_0));
OUTREG32(&g_pIntcRegs->ulINTC_MIR_SET0, 1 << IRQ_GPIO1_MPU);
CLRREG32(&g_pGPIORegs[0]->ulGPIO_IRQENABLE1, 1<<(irq - IRQ_GPIO_0)); // mask IRQ
OUTREG32(&g_pGPIORegs[0]->ulGPIO_IRQSTATUS1, 1<<(irq - IRQ_GPIO_0)); // clear IRQ
} else if (irq < IRQ_GPIO_64) {
OALMSG(OAL_INTR, (
L"OALIntrDisableIrqs(Irq GPIO2 %d)\r\n", irq - IRQ_GPIO_32));
OUTREG32(&g_pIntcRegs->ulINTC_MIR_SET0, 1 << IRQ_GPIO2_MPU);
CLRREG32(&g_pGPIORegs[1]->ulGPIO_IRQENABLE1, 1<<(irq - IRQ_GPIO_32)); // mask IRQ
OUTREG32(&g_pGPIORegs[1]->ulGPIO_IRQSTATUS1, 1<<(irq - IRQ_GPIO_32)); // clear IRQ
} else if (irq < IRQ_GPIO_96) {
OALMSG(OAL_INTR, (
L"OALIntrDisableIrqs(Irq GPIO3 %d)\r\n", irq - IRQ_GPIO_64));
OUTREG32(&g_pIntcRegs->ulINTC_MIR_SET0, 1 << IRQ_GPIO3_MPU);
CLRREG32(&g_pGPIORegs[2]->ulGPIO_IRQENABLE1, 1<<(irq - IRQ_GPIO_64)); // mask IRQ
OUTREG32(&g_pGPIORegs[2]->ulGPIO_IRQSTATUS1, 1<<(irq - IRQ_GPIO_64)); // clear IRQ
} else if (irq < IRQ_GPIO_128) {
OALMSG(OAL_INTR, (
L"OALIntrDisableIrqs(Irq GPIO4 %d)\r\n", irq - IRQ_GPIO_96));
OUTREG32(&g_pIntcRegs->ulINTC_MIR_SET1, 1 << (IRQ_GPIO4_MPU-32));
CLRREG32(&g_pGPIORegs[3]->ulGPIO_IRQENABLE1, 1<<(irq - IRQ_GPIO_96)); // mask IRQ
OUTREG32(&g_pGPIORegs[3]->ulGPIO_IRQSTATUS1, 1<<(irq - IRQ_GPIO_96)); // clear IRQ
} else if (irq < IRQ_GPIO_160) {
OALMSG(OAL_INTR, (
L"OALIntrDisableIrqs(Irq GPIO5 %d)\r\n", irq - IRQ_GPIO_128));
OUTREG32(&g_pIntcRegs->ulINTC_MIR_SET1, 1 << (IRQ_GPIO5_MPU-32));
CLRREG32(&g_pGPIORegs[4]->ulGPIO_IRQENABLE1, 1<<(irq - IRQ_GPIO_128)); // mask IRQ
OUTREG32(&g_pGPIORegs[4]->ulGPIO_IRQSTATUS1, 1<<(irq - IRQ_GPIO_128)); // clear IRQ
} else if (irq < IRQ_GPIO_192) {
OALMSG(OAL_INTR, (
L"OALIntrDisableIrqs(Irq GPIO6 %d)\r\n", irq - IRQ_GPIO_160));
OUTREG32(&g_pIntcRegs->ulINTC_MIR_SET1, 1 << (IRQ_GPIO6_MPU-32));
CLRREG32(&g_pGPIORegs[5]->ulGPIO_IRQENABLE1, 1<<(irq - IRQ_GPIO_160)); // mask IRQ
OUTREG32(&g_pGPIORegs[5]->ulGPIO_IRQSTATUS1, 1<<(irq - IRQ_GPIO_160)); // clear IRQ
}
}
OALMSG(OAL_INTR&&OAL_FUNC, (L"-OALIntrDisableIrqs\r\n"));
}
//------------------------------------------------------------------------------
//
// Function: OALIntrDoneIrqs
//
VOID OALIntrDoneIrqs(UINT32 count, const UINT32 *pIrqs)
{
UINT32 irq, i;
for (i = 0; i < count; i++) {
irq = pIrqs[i];
if (irq < 32) {
OUTREG32(&g_pIntcRegs->ulINTC_MIR_CLEAR0, 1 << irq);
} else if (irq < 64) {
OUTREG32(&g_pIntcRegs->ulINTC_MIR_CLEAR1, 1 << (irq - 32));
} else if (irq < 96) {
OUTREG32(&g_pIntcRegs->ulINTC_MIR_CLEAR2, 1 << (irq - 64));
} else if (irq < IRQ_GPIO_32) {
OALMSG(OAL_INTR, (L"OALIntrDoneIrqs(Irq GPIO1 %d)\r\n", irq - IRQ_GPIO_0));
OUTREG32(&g_pIntcRegs->ulINTC_MIR_CLEAR0, 1 << IRQ_GPIO1_MPU);
OUTREG32(&g_pGPIORegs[0]->ulGPIO_IRQSTATUS1, 1<<(irq - IRQ_GPIO_0)); // clear IRQ
SETREG32(&g_pGPIORegs[0]->ulGPIO_IRQENABLE1, 1<<(irq - IRQ_GPIO_0)); // unmask IRQ
} else if (irq < IRQ_GPIO_64) {
OALMSG(OAL_INTR, (L"OALIntrDoneIrqs(Irq GPIO2 %d)\r\n", irq - IRQ_GPIO_32));
OUTREG32(&g_pIntcRegs->ulINTC_MIR_CLEAR0, 1 << IRQ_GPIO2_MPU);
OUTREG32(&g_pGPIORegs[1]->ulGPIO_IRQSTATUS1, 1<<(irq - IRQ_GPIO_32)); // clear IRQ
SETREG32(&g_pGPIORegs[1]->ulGPIO_IRQENABLE1, 1<<(irq - IRQ_GPIO_32)); // unmask IRQ
} else if (irq < IRQ_GPIO_96) {
OALMSG(OAL_INTR, (L"OALIntrDoneIrqs(Irq GPIO3 %d)\r\n", irq - IRQ_GPIO_64));
OUTREG32(&g_pIntcRegs->ulINTC_MIR_CLEAR0, 1 << IRQ_GPIO3_MPU);
OUTREG32(&g_pGPIORegs[2]->ulGPIO_IRQSTATUS1, 1<<(irq - IRQ_GPIO_64)); // clear IRQ
SETREG32(&g_pGPIORegs[2]->ulGPIO_IRQENABLE1, 1<<(irq - IRQ_GPIO_64)); // unmask IRQ
} else if (irq < IRQ_GPIO_128) {
OALMSG(OAL_INTR, (L"OALIntrDoneIrqs(Irq GPIO4 %d)\r\n", irq - IRQ_GPIO_96));
OUTREG32(&g_pIntcRegs->ulINTC_MIR_CLEAR1, 1 << (IRQ_GPIO4_MPU-32));
OUTREG32(&g_pGPIORegs[3]->ulGPIO_IRQSTATUS1, 1<<(irq - IRQ_GPIO_96)); // clear IRQ
SETREG32(&g_pGPIORegs[3]->ulGPIO_IRQENABLE1, 1<<(irq - IRQ_GPIO_96)); // unmask IRQ
} else if (irq < IRQ_GPIO_160) {
OALMSG(OAL_INTR, (L"OALIntrDoneIrqs(Irq GPIO5 %d)\r\n", irq - IRQ_GPIO_128));
OUTREG32(&g_pIntcRegs->ulINTC_MIR_CLEAR1, 1 << (IRQ_GPIO5_MPU-32));
OUTREG32(&g_pGPIORegs[4]->ulGPIO_IRQSTATUS1, 1<<(irq - IRQ_GPIO_128)); // clear IRQ
SETREG32(&g_pGPIORegs[4]->ulGPIO_IRQENABLE1, 1<<(irq - IRQ_GPIO_128)); // unmask IRQ
} else if (irq < IRQ_GPIO_192) {
OALMSG(OAL_INTR, (L"OALIntrDoneIrqs(Irq GPIO6 %d)\r\n", irq - IRQ_GPIO_160));
OUTREG32(&g_pIntcRegs->ulINTC_MIR_CLEAR1, 1 << (IRQ_GPIO6_MPU-32));
OUTREG32(&g_pGPIORegs[5]->ulGPIO_IRQSTATUS1, 1<<(irq - IRQ_GPIO_160)); // clear IRQ
SETREG32(&g_pGPIORegs[5]->ulGPIO_IRQENABLE1, 1<<(irq - IRQ_GPIO_160)); // unmask IRQ
}
}
OALMSG(OAL_INTR&&OAL_VERBOSE, (L"-OALIntrDoneIrq\r\n"));
}
//------------------------------------------------------------------------------
//
// Function: OEMInterruptHandler
//
// This is interrupt handler implementation.
//
UINT32 OEMInterruptHandler()
{
UINT32 irq = OAL_INTR_IRQ_UNDEFINED;
UINT32 sysIntr = SYSINTR_NOP;
UINT32 data, mask;
// Get pending interrupt
irq = INREG32(&g_pIntcRegs->ulINTC_SIR_IRQ);
// Check if this is timer IRQ
if (irq == g_oalTimerIrq) {
// Call timer interrupt handler
sysIntr = OALTimerIntrHandler();
// We are done with interrupt
OALIntrDoneIrqs(1, &irq);
}
else if (irq != OAL_INTR_IRQ_UNDEFINED)
{
#ifdef OAL_ILTIMING
if (g_oalILT.active) g_oalILT.interrupts++;
#endif
if (irq == IRQ_GPIO1_MPU) {
OALMSG(OAL_INTR, (L"OEMInterruptHandler(Irq GPIO1)\r\n"));
irq = IRQ_GPIO_0;
OUTREG32(&g_pIntcRegs->ulINTC_MIR_SET0, 1 << IRQ_GPIO1_MPU);
// If it is interrupt from GPIOx, find which one, mask and clear it..
if ((data = INREG32(&g_pGPIORegs[0]->ulGPIO_IRQSTATUS1)) != 0) {
for (mask = 1; mask != 0; mask <<= 1, irq++) {
if ((mask & data) != 0) break;
}
OUTREG32(&g_pGPIORegs[0]->ulGPIO_CLEARIRQENABLE1, mask); // mask IRQ
OALMSG(OAL_INTR, (L"GPIO Interrupt irq - %d\r\n",irq ));
}
} else if (irq == IRQ_GPIO2_MPU) {
OALMSG(OAL_INTR, (L"OEMInterruptHandler(Irq GPIO2)\r\n"));
irq = IRQ_GPIO_32;
OUTREG32(&g_pIntcRegs->ulINTC_MIR_SET0, 1 << IRQ_GPIO2_MPU);
// If it is interrupt from GPIOx, find which one, mask it..
if ((data = INREG32(&g_pGPIORegs[1]->ulGPIO_IRQSTATUS1)) != 0) {
for (mask = 1; mask != 0; mask <<= 1, irq++) {
if ((mask & data) != 0) break;
}
OUTREG32(&g_pGPIORegs[1]->ulGPIO_CLEARIRQENABLE1, mask); // mask IRQ
OALMSG(OAL_INTR, (L"GPIO Interrupt irq - %d\r\n",irq ));
}
} else if (irq == IRQ_GPIO3_MPU) {
OALMSG(OAL_INTR, (L"OEMInterruptHandler(Irq GPIO3)\r\n"));
irq = IRQ_GPIO_64;
OUTREG32(&g_pIntcRegs->ulINTC_MIR_SET0, 1 << IRQ_GPIO3_MPU);
// If it is interrupt from GPIOx, find which one, mask it..
if ((data = INREG32(&g_pGPIORegs[2]->ulGPIO_IRQSTATUS1)) != 0) {
for (mask = 1; mask != 0; mask <<= 1, irq++) {
if ((mask & data) != 0) break;
}
OUTREG32(&g_pGPIORegs[2]->ulGPIO_CLEARIRQENABLE1, mask); // mask IRQ
OALMSG(OAL_INTR, (L"GPIO Interrupt irq - %d\r\n",irq ));
}
} else if (irq == IRQ_GPIO4_MPU) {
OALMSG(OAL_INTR, (L"OEMInterruptHandler(Irq GPIO4)\r\n"));
irq = IRQ_GPIO_96;
OUTREG32(&g_pIntcRegs->ulINTC_MIR_SET1, 1 << (IRQ_GPIO4_MPU - 32));
// If it is interrupt from GPIOx, find which one, mask it..
if ((data = INREG32(&g_pGPIORegs[3]->ulGPIO_IRQSTATUS1)) != 0) {
for (mask = 1; mask != 0; mask <<= 1, irq++) {
if ((mask & data) != 0) break;
}
OUTREG32(&g_pGPIORegs[3]->ulGPIO_CLEARIRQENABLE1, mask); // mask IRQ
OALMSG(OAL_INTR, (L"GPIO Interrupt irq - %d\r\n",irq ));
}
} else if (irq == IRQ_GPIO5_MPU) {
OALMSG(OAL_INTR, (L"OEMInterruptHandler(Irq GPIO5)\r\n"));
irq = IRQ_GPIO_128;
OUTREG32(&g_pIntcRegs->ulINTC_MIR_SET1, 1 << (IRQ_GPIO5_MPU - 32));
// If it is interrupt from GPIOx, find which one, mask it..
if ((data = INREG32(&g_pGPIORegs[4]->ulGPIO_IRQSTATUS1)) != 0) {
for (mask = 1; mask != 0; mask <<= 1, irq++) {
if ((mask & data) != 0) break;
}
OUTREG32(&g_pGPIORegs[4]->ulGPIO_CLEARIRQENABLE1, mask); // mask IRQ
OALMSG(OAL_INTR, (L"GPIO Interrupt irq - %d\r\n",irq ));
}
} else if (irq == IRQ_GPIO6_MPU) {
OALMSG(OAL_INTR, (L"OEMInterruptHandler(Irq GPIO6)\r\n"));
irq = IRQ_GPIO_160;
OUTREG32(&g_pIntcRegs->ulINTC_MIR_SET1, 1 << (IRQ_GPIO6_MPU - 32));
// If it is interrupt from GPIOx, find which one, mask it..
if ((data = INREG32(&g_pGPIORegs[5]->ulGPIO_IRQSTATUS1)) != 0) {
for (mask = 1; mask != 0; mask <<= 1, irq++) {
if ((mask & data) != 0) break;
}
OUTREG32(&g_pGPIORegs[5]->ulGPIO_CLEARIRQENABLE1, mask); // mask IRQ
OALMSG(OAL_INTR, (L"GPIO Interrupt irq - %d\r\n",irq ));
}
} else if (irq < 32) {
OALMSG(OAL_INTR, (L"OEMInterruptHandler(Irq %d)\r\n", irq));
SETPORT32(&g_pIntcRegs->ulINTC_MIR0, 1 << irq);
} else if (irq < 64) {
OALMSG(OAL_INTR, (L"OEMInterruptHandler(Irq %d)\r\n", irq));
SETPORT32(&g_pIntcRegs->ulINTC_MIR1, 1 << (irq - 32));
} else if (irq < 96) {
OALMSG(OAL_INTR, (L"OEMInterruptHandler(Irq %d)\r\n", irq));
SETPORT32(&g_pIntcRegs->ulINTC_MIR2, 1 << (irq - 64));
} else if (irq < 128) {
OALMSG(OAL_INTR, (L"OEMInterruptHandler(Irq %d)\r\n", irq));
SETPORT32(&g_pIntcRegs->ulINTC_MIR2, 1 << (irq - 96));
} else if (irq < 160) {
OALMSG(OAL_INTR, (L"OEMInterruptHandler(Irq %d)\r\n", irq));
SETPORT32(&g_pIntcRegs->ulINTC_MIR2, 1 << (irq - 128));
} else {
OALMSG(OAL_INTR, (L"OEMInterruptHandler(Irq UNKNOWNNON %d)\r\n", irq));
}
// We don't assume IRQ sharing, use static mapping
sysIntr = OALIntrTranslateIrq(irq);
OALMSG(OAL_INTR, (L"OALIntrTranslateIrq(%d)=%d\r\n",irq,sysIntr));
}
else
{
OALMSG( 1, (L"undefined IRQ interrupt - %d\r\n",irq));
}
//Acknowledge the existing IRQ and set the INTC for receiving new IRQ interrupts
SETREG32(&g_pIntcRegs->ulINTC_CONTROL,1);
#ifdef OAL_FAKE_IDLE
// Set flag for fake wake/idle
if (sysIntr != SYSINTR_NOP) g_oalLastSysIntr = sysIntr;
#endif
return sysIntr;
}
//------------------------------------------------------------------------------
//
// Function: OALIntrIsIrqPending
//
// This function checks if the given interrupt is pending.
//
BOOL OALIntrIsIrqPending(UINT32 irq)
{
BOOL rc = FALSE;
if (irq < 32) {
rc = INREG32(&g_pIntcRegs->ulINTC_ITR0) & (1 << irq);
} else if (irq < 64) {
rc = INREG32(&g_pIntcRegs->ulINTC_ITR1) & (1 << (irq - 32));
} else if (irq < 96) {
rc = INREG32(&g_pIntcRegs->ulINTC_ITR2) & (1 << (irq - 64));
}
return (rc != 0);
}
//------------------------------------------------------------------------------
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