addrtab_cfg.inc

来自「Windows CE 6.0 BSP for the Beagle Board.」· INC 代码 · 共 56 行

;
; Copyright (c) Microsoft Corporation.  All rights reserved.
; Copyright (c) Special Computing.  All rights reserved.
;
;------------------------------------------------------------------------------
;
;  File:  addrtab_cfg.inc
;
;  This file is used to define g_oalAddressTable. This table is passed to
;  KernelStart to estabilish physical to virtual memory mapping. This table
;  is used also in memory OAL module to map between physical and virtual
;  memory addresses via OALPAtoVA/OALVAtoPA functions.
;
;  The config.bib file defines image memory layout ant it contains virtual
;  cached memory addresses which must be synchronized with g_oalAddressTable.
;  With each table change make sure that those constant are still valid.
;------------------------------------------------------------------------------
;  Export Definition

        EXPORT  g_oalAddressTable[DATA]

;------------------------------------------------------------------------------
;  Table format: cached address, physical address, size
;
;g_oalAddressTable
;
;        DCD 0x84000000, 0x80000000,  32           ; SDRAM (lower 32MB mapped)
;        DCD 0x86000000, 0xA0000000,  32           ; SDRAM (higher 32MB mapped)
;        DCD 0x80000000, 0x00000000,  64           ; CS0 
;        DCD 0x88000000, 0x40200000,  4            ; ISRAM 
;        DCD 0x88600000, 0x48000000,  1            ; L4 Peripherals
;        DCD 0x88E00000, 0x68000000,  1            ; L3 Peripherals
;        DCD 0x00000000, 0x00000000,  0            ; End of Table.
;
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
;  Table format: cached address, physical address, size

g_oalAddressTable

        DCD 0x90000000, 0x00000000,  256          ; CS0
        DCD 0x88000000, 0x40000000,  1            ; Boot ROM 
        DCD 0x88100000, 0x40200000,  1            ; ISRAM 
        DCD 0x88200000, 0x48000000,  17           ; L4 Core/Wakeup/Per (INTC)
        DCD 0x89300000, 0x50000000,  1            ; SGX
        DCD 0x89400000, 0x54000000,  8            ; L4 EMU
        DCD 0x89C00000, 0x5C000000,  48           ; IVA
        DCD 0x8CC00000, 0x68000000,  1            ; L3 Control
        DCD 0x8CD00000, 0x6C000000,  48           ; L3 SMS/SDRC/GPMC
        DCD 0x80000000, 0x80000000,  128          ; SDRAM
        DCD 0x00000000, 0x00000000,  0            ; End of Table.

;------------------------------------------------------------------------------

        END