📄 bsp_ctrlpadconf_cfg.inc
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;
; Copyright (c) Microsoft Corporation. All rights reserved.
;
;
; Use of this sample source code is subject to the terms of the Microsoft
; license agreement under which you licensed this sample source code. If
; you did not accept the terms of the license agreement, you are not
; authorized to use this sample source code. For the terms of the license,
; please see the license agreement between you and Microsoft or, if applicable,
; see the LICENSE.RTF on your install media or the root of your tools installation.
; THE SAMPLE SOURCE CODE IS PROVIDED "AS IS", WITH NO WARRANTIES.
;
;------------------------------------------------------------------------------
;
; File: bsp_ctrlpadconf_cfg.inc
;
; This file defines initial values for OMAP2420 config registers. Those values
; are used in hardware initialization to switch SoC to required configuration.
; Refer to OMAP2420 configuration module documentation for register
; description.
;
;------------------------------------------------------------------------------
;
; Define: BSP_PADCONF_XXX
;
; 31-29 reserved (xxx),
; 28 pulltype select_3(x),
; 27 pullud enable_3 (x),
; 26-24 muxmode_3 (xxx),
; 23-21 reserved (xxx),
; 20 pulltype select_2(x),
; 19 pullud enable_2 (x),
; 18-16 muxmode_2 (xxx),
; 15-13 reserved (xxx),
; 12 pulltype select_1(x),
; 11 pullud enable_1 (x),
; 10-8 muxmode_1 (xxx),
; 7-5 reserved (xxx),
; 4 pulltype select_0(x),
; 3 pullud enable_0 (x),
; 2-0 muxmode_0 (xxx)
PUP EQU 0x18 ;Pull Up resistor enabled
PDN EQU 0x8 ;Pull Down resistor enabled
BYTE0 EQU 0
BYTE1 EQU 0x8
BYTE2 EQU 0x10
BYTE3 EQU 0x18
;offset 0x30 ball D10,sdrc_ba1 ball D11,sdrc_a12 ball B4,gpio1 ball B3,sdrc_a14
BSP_PADCONF_SDRC_A14 EQU (0 << BYTE3) + (0 << BYTE2) + ((3 + PDN) << BYTE1) + ((7 + PDN) << BYTE0)
;BSP_PADCONF_SDRC_BA0 EQU; offset 0x34
;BSP_PADCONF_SDRC_A8 EQU; offset 0x38
;BSP_PADCONF_SDRC_A4 EQU; offset 0x3C
;BSP_PADCONF_SDRC_A0 EQU; offset 0x40
;BSP_PADCONF_SDRC_STK_D16 EQU; offset 0x50
;BSP_PADCONF_SDRC_D28 EQU; offset 0x54
;BSP_PADCONF_SDRC_D24 EQU; offset 0x58
;BSP_PADCONF_SDRC_D20 EQU; offset 0x5C
;BSP_PADCONF_SDRC_D16 EQU; offset 0x60
;BSP_PADCONF_SDRC_D12 EQU; offset 0x64
;BSP_PADCONF_SDRC_D8 EQU; offset 0x68
;BSP_PADCONF_SDRC_D4 EQU; offset 0x6C
;BSP_PADCONF_SDRC_D0 EQU; offset 0x70
;BSP_PADCONF_GPMC_A7 EQU; offset 0x74
;BSP_PADCONF_GPMC_A3 EQU; offset 0x78
;BSP_PADCONF_GPMC_D14 EQU; offset 0x7C
;BSP_PADCONF_GPMC_D10 EQU; offset 0x80
;BSP_PADCONF_GPMC_D6 EQU; offset 0x84
;BSP_PADCONF_GPMC_D2 EQU; offset 0x88
;offset 0x8C ball N2,gpmc_cs3 ball E2,gpmc_cs2 ball N8,gpmc_cs1 ball L4,gpmc_cs0
BSP_PADCONF_GPMC_NCS0 EQU ((1 + PUP) << BYTE3) + (0 << BYTE2) + (0 << BYTE1) + (0 << BYTE0)
;BSP_PADCONF_GPMC_NCS4 EQU; offset 0x90
;BSP_PADCONF_GPMC_NADV_ALE EQU; offset 0x94
;BSP_PADCONF_GPMC_NBE1 EQU; offset 0x98
;offset 0x9C ball B14,sdrc_nclk ball C14,sdrc_clk ball P1,GPIO_35 ball M1,gpmc_wait2
BSP_PADCONF_GPMC_WAIT2 EQU (0 << BYTE3) + (0 << BYTE2) + ((3 + PUP) << BYTE1) + ((7 + PUP) << BYTE0)
;offset 0xA0 ball B13,sdrc_ncs1 ball D13,sdrc_cke0 ball C12,sdrc_cke1 ball D12,sdrc_ncs0
BSP_PADCONF_SDRC_NCS0 EQU (0 << BYTE3) + (0 << BYTE2) + (0 << BYTE1) + (0 << BYTE0)
;BSP_PADCONF_SDRC_NRAS EQU; offset 0xA4
;BSP_PADCONF_SDRC_DM1 EQU; offset 0xA8
;BSP_PADCONF_SDRC_STK_DM1 EQU; offset 0xAC
;offset 0xB0 ball Y7,dss_d0 ball B18,sdrc_dqs3 ball D16,sdrc_dqs2 ball G9,sdrc_dqs1
BSP_PADCONF_SDRC_DQS1 EQU (0 << BYTE3) + ((0 + PDN) << BYTE2) + ((0 + PDN) << BYTE1) + ((0 + PDN) << BYTE0)
;offset 0xB4 ball W8,dss_d4 ball Y8,dss_d3 ball V8,dss_d2 ball P10,dss_d1
BSP_PADCONF_DSS_D1 EQU (0 << BYTE3) + (0 << BYTE2) + (0 << BYTE1) + (0 << BYTE0)
;offset 0xB8 ball W9,dss_d8 ball V9,dss_d7 ball Y9,dss_d6 ball R10,dss_d5
BSP_PADCONF_DSS_D5 EQU (0 << BYTE3) + (0 << BYTE2) + (0 << BYTE1) + (0 << BYTE0)
;offset 0xBC ball W10,dss_d12 ball Y10,dss_d11 ball V10,dss_d10 ball P11,dss_d9
BSP_PADCONF_DSS_D9 EQU (0 << BYTE3) + (0 << BYTE2) + (0 << BYTE1) + (0 << BYTE0)
;offset 0xC0 ball P12,dss_d16 ball W11,dss_d15 ball V11,dss_d14 ball R11,dss_d13
BSP_PADCONF_DSS_D13 EQU (0 << BYTE3) + (0 << BYTE2) + (0 << BYTE1) + (0 << BYTE0)
;offset 0xC4 ball L20,uart1_tx ball H21,uart1_rts ball D21,uart1_cts ball R12,dss_d17
BSP_PADCONF_DSS_D17 EQU (0 << BYTE3) + (0 << BYTE2) + ((0 + PUP) << BYTE1) + (0 << BYTE0)
;offset 0xC8 ball W6,dss_pclk ball P21,mcbsp2_clkx ball M21,mcbsp2_dr ball T21,uart1_rx
BSP_PADCONF_UART1_RX EQU (0 << BYTE3) + (3 << BYTE2) + ((3 + PUP) << BYTE1) + ((0 + PUP) << BYTE0)
;offset 0xCC ball V6,cam_d9 ball W7,dss_acbias ball Y6,dss_hsync ball V7,dss_vsync
BSP_PADCONF_DSS_VSYNC EQU ((0 + PDN) << BYTE3) + (0 << BYTE2) + (0 << BYTE1) + (0 << BYTE0)
;offset 0xD0 ball V4,cam_d5 ball W3,cam_d6 ball Y2,cam_d7 ball Y4,cam_d8
BSP_PADCONF_CAM_D8 EQU ((0 + PDN) << BYTE3) + ((0 + PDN) << BYTE2) + ((0 + PDN) << BYTE1) + ((0 + PDN) << BYTE0)
;offset 0xD4 ball V2,cam_d1 ball V3,cam_d2 ball U4,cam_d3 ball W2,cam_d4
BSP_PADCONF_CAM_D4 EQU ((0 + PDN) << BYTE3) + ((0 + PDN) << BYTE2) + ((0 + PDN) << BYTE1) + ((0 + PDN) << BYTE0)
;offset 0xD8 ball V5,cam_lclk ball U2,cam_vs ball T3,cam_hs ball T4,cam_d0
BSP_PADCONF_CAM_D0 EQU ((0 + PDN) << BYTE3) + ((0 + PDN) << BYTE2) + ((0 + PDN) << BYTE1) + ((0 + PDN) << BYTE0)
;offset 0xDC ball P13,GPIO.61 ball V12,GPIO.25 ball W12,ssi1_dat_tx ball U3,cam_xclk
BSP_PADCONF_CAM_XCLK EQU ((3 + PDN) << BYTE3) + ((3 + PDN) << BYTE2) + ((7 + PUP) << BYTE1) + ((0 + PDN) << BYTE0)
;offset 0xE0 ball V13,EAC.MD_DOUT ball W13,EAC.MD_DIN ball Y12,EAC.MD_SCLK ball R13,gpio_62
BSP_PADCONF_GPIO_62 EQU (1 << BYTE3) + (1 << BYTE2) + (1 << BYTE1) + ((0 + PDN) << BYTE0)
;offset 0xE4 ball AA4,GPIO.15 ball AA6,vlynq_rx1 ball AA10,GPIO.13 ball Y13,EAC.MD_FS
BSP_PADCONF_SSI1_WAKE EQU (3 << BYTE3) + ((7 + PDN) << BYTE2) + ((3 + PDN) << BYTE1) + (1 << BYTE0)
; offset 0xE8 ball V19,uart2_cts ball AA8,GPIO.58 ball AA12,GPIO.17 ball Y11,GPIO.16
BSP_PADCONF_VLYNQ_TX1 EQU ((7 + PUP) << BYTE3) + (3 << BYTE2) + (3 << BYTE1) + ((3 + PDN) << BYTE0)
; offset 0xEC ball R8,eac_bt_sclk ball P15,uart2_rx ball N14,uart2_tx ball W20,uart2_rts
BSP_PADCONF_UART2_RTS EQU ((0 + PDN) << BYTE3) + ((7 + PUP) << BYTE2) + ((7 + PUP) << BYTE1) + ((7 + PUP) << BYTE0)
; offset 0xF0 ball G19,mmc_clko ball W4,eac_bt_dout ball Y3,eac_bt_din ball P9,eac_bt_fs
BSP_PADCONF_EAC_BT_FS EQU (0 << BYTE3) + (0 << BYTE2) + (0 << BYTE1) + (0 << BYTE0)
; offset 0xF4 ball E19,mmc_dat2 ball H14,mmc_dat1 ball F20,mmc_dat0 ball H18,mmc_cmd
BSP_PADCONF_MMC_CMD EQU (0 << BYTE3) + (0 << BYTE2) + (0 << BYTE1) + (0 << BYTE0)
; offset 0xF8 ball F18,mmc_dat2 ball E20,mmc_dat1 ball F19,mmc_dat0 ball D19,mmc_cmd
BSP_PADCONF_MMC_DAT3 EQU (0 << BYTE3) + (0 << BYTE2) + (0 << BYTE1) + (0 << BYTE0)
; offset 0xFC ball U18,spi1_clk ball H15,mmc_clki ball G18,mmc_cmd_dir ball E18,mmc_dat_dir3
BSP_PADCONF_MMC_DAT_DIR3 EQU ((0 + PDN) << BYTE3) + (0 << BYTE2) + (0 << BYTE1) + (0 << BYTE0)
; offset 0x100 ball N15,spi1_cs1 ball U19,spi1_cs0 ball T18,spi1_somi ball V20,spi1_simo
BSP_PADCONF_SPI1_SIMO EQU (0 << BYTE3) + ((0 + PUP) << BYTE2) + ((0 + PDN) << BYTE1) + (0 << BYTE0)
; offset 0x104 ball R19,GPIO.89 ball T19,GPIO.88 ball U21,spi1_cs3 ball R18,spi1_cs2
BSP_PADCONF_SPI1_NCS2 EQU ((3 + PUP) << BYTE3) + ((3 + PUP) << BYTE2) + ((7 + PUP) << BYTE1) + (0 << BYTE0)
; offset 0x108 ball P20,GPIO.93 ball M15,GPIO.92 ball M14,GPIO.91 ball R20,GPIO.90
BSP_PADCONF_SPI2_SOMI EQU ((3 + PUP) << BYTE3) + ((3 + PDN) << BYTE2) + (3 << BYTE1) + (3 << BYTE0)
; offset 0x10C ball L14,GPIO.97 ball M18,GPIO.96 ball P18,GPIO.95 ball P19,mcbsp1_dx
BSP_PADCONF_MCBSP1_DX EQU (3 << BYTE3) + (3 << BYTE2) + ((3 + PUP) << BYTE1) + ((7 + PDN)<< BYTE0)
; offset 0x110 ball J15,i2c2_scl ball L15,i2c1_sda ball M19,i2c1_scl ball N19,GPIO.98
BSP_PADCONF_MCBSP1_CLKX EQU ((7 + PUP) << BYTE3) + ((0 + PUP) << BYTE2) + ((0 + PUP) << BYTE1) + ((3 + PUP) << BYTE0)
; offset 0x114 ball L19,GPIO.103 ball L18,GPIO.102 ball N18,HDQ ball H19,i2c2_sda
BSP_PADCONF_I2C2_SDA EQU ((3 + PUP) << BYTE3) + ((3 + PDN) << BYTE2) + ((0 + PUP) << BYTE1) + ((7 + PUP) << BYTE0)
;offset 0x118 ball AA18,tv_vref ball AA16,tv_cvbs ball K14,uart3_rx_irrx ball K15,uart3_tx_irrx
BSP_PADCONF_UART3_TX_IRTX EQU (0 << BYTE3) + (0 << BYTE2) + (0 << BYTE1) + (0 << BYTE0)
; offset 0x11C ball K20,usb0_vm ball J19,usb0_vp ball J20,usb0_puen ball AA14,tv_rref
;BSP_PADCONF_TV_RREF EQU (0 << BYTE3) + (0 << BYTE2) + (0 << BYTE1) + (0 << BYTE0)
; offset 0x120 ball K18,usb0_dat ball J14,usb0_se0 ball K19,usb0_txen ball J18,usb0_rcv
;BSP_PADCONF_USB0_RCV EQU (0 << BYTE3) + (0 << BYTE2) + (0 << BYTE1) + (0 << BYTE0)
; offset 0x124 ball V15,mcbsp2_dx ball W15,mcbsp2_dr ball R14,mcbsp2_fsx ball Y15,mcbsp2_clkx
BSP_PADCONF_EAC_AC_SCLK EQU (1 << BYTE3) + (1 << BYTE2) + (1 << BYTE1) + (1 << BYTE0)
; offset 0x128 ball Y16,sys_nreswarm ball Y14,sys_nrespwron ball W16,GPIO.118 ball V14,GPIO.117
BSP_PADCONF_EAC_AC_MCLK EQU ((0 + PUP) << BYTE3) + (0 << BYTE2) + ((3 + PUP) << BYTE1) + ((3 + PDN) << BYTE0)
; offset 0x12C ball Y5,gpio_120 ball W5,gpio_119 ball Y20,sys_nvmode ball W19,sys_nirq
BSP_PADCONF_SYS_NIRQ EQU (7 << BYTE3) + (7 << BYTE2) + (0 << BYTE1) + ((0 + PUP) << BYTE0)
; offset 0x130 ball Y18,sys_xtalin ball Y17,sys_32k ball P8,GPIO.122 ball R9,gpio_121
BSP_PADCONF_GPIO_121 EQU (0 << BYTE3) + (0 << BYTE2) + (0 << BYTE1) + (7 << BYTE0)
; offset 0x134 ball W14,sys_clkout ball AA17,sys_clkreq ball V17,GPIO.36 ball V16,sys_xtalout
BSP_PADCONF_SYS_XTALOUT EQU (0 << BYTE3) + ((7 + PUP) << BYTE2) + (0 << BYTE1) + (0 << BYTE0)
; offset 0x138 ball AA21,jtag_emu1 ball P14,GPIO.125 ball V18,GPIO.88 ball E5,GPIO.6
BSP_PADCONF_GPIO_6 EQU ((7 + PUP) << BYTE3) + ((0 + PDN) << BYTE2) + ((0 + PUP) << BYTE1) + ((0 + PUP) << BYTE0)
; offset 0x13C
;BSP_PADCONF_JTAG_EMU0 EQU
; offset 0x140
;BSP_PADCONF_JTAG_TMS EQU
END
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