cache_builder.cc

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/*
 * Copyright (c) 2003, 2004, 2005
 * The Regents of The University of Michigan
 * All Rights Reserved
 *
 * This code is part of the M5 simulator, developed by Nathan Binkert,
 * Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
 * from Ron Dreslinski, Dave Greene, Lisa Hsu, Kevin Lim, Ali Saidi,
 * and Andrew Schultz.
 *
 * Permission is granted to use, copy, create derivative works and
 * redistribute this software and such derivative works for any
 * purpose, so long as the copyright notice above, this grant of
 * permission, and the disclaimer below appear in all copies made; and
 * so long as the name of The University of Michigan is not used in
 * any advertising or publicity pertaining to the use or distribution
 * of this software without specific, written prior authorization.
 *
 * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
 * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND
 * WITHOUT WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE. THE REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE
 * LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT,
 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM
 * ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN
 * IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH
 * DAMAGES.
 */

/**
 * @file
 * Simobject instatiation of caches.
 */
#include <vector>

// Must be included first to determine which caches we want
#include "mem/config/cache.hh"
#include "mem/config/compression.hh"

#include "mem/cache/base_cache.hh"
#include "mem/cache/cache.hh"
#include "mem/bus/bus.hh"
#include "mem/cache/coherence/coherence_protocol.hh"
#include "sim/builder.hh"

// Tag Templates
#if defined(USE_CACHE_LRU)
#include "mem/cache/tags/lru.hh"
#endif

#if defined(USE_CACHE_FALRU)
#include "mem/cache/tags/fa_lru.hh"
#endif

#if defined(USE_CACHE_IIC)
#include "mem/cache/tags/iic.hh"
#endif

#if defined(USE_CACHE_SPLIT)
#include "mem/cache/tags/split.hh"
#endif

#if defined(USE_CACHE_SPLIT_LIFO)
#include "mem/cache/tags/split_lifo.hh"
#endif

// Compression Templates
#include "base/compression/null_compression.hh"
#if defined(USE_LZSS_COMPRESSION)
#include "base/compression/lzss_compression.hh"
#endif

// CacheTags Templates
#include "mem/cache/tags/cache_tags.hh"

// MissQueue Templates
#include "mem/cache/miss/miss_queue.hh"
#include "mem/cache/miss/blocking_buffer.hh"

// Coherence Templates
#include "mem/cache/coherence/uni_coherence.hh"
#include "mem/cache/coherence/simple_coherence.hh"

// Bus Interfaces
#include "mem/bus/slave_interface.hh"
#include "mem/bus/master_interface.hh"
#include "mem/memory_interface.hh"

#include "mem/trace/mem_trace_writer.hh"

//#include "mem/cache/prefetch/ghb_prefetcher.hh"
#include "mem/cache/prefetch/tagged_prefetcher.hh"
//#include "mem/cache/prefetch/stride_prefetcher.hh"


using namespace std;

#ifndef DOXYGEN_SHOULD_SKIP_THIS

BEGIN_DECLARE_SIM_OBJECT_PARAMS(BaseCache)

    Param<int> size;
    Param<int> assoc;
    Param<int> block_size;
    Param<int> latency;
    Param<int> mshrs;
    Param<int> tgts_per_mshr;
    Param<int> write_buffers;
    Param<bool> prioritizeRequests;
    SimObjectParam<Bus *> in_bus;
    SimObjectParam<Bus *> out_bus;
    Param<bool> do_copy;
    SimObjectParam<CoherenceProtocol *> protocol;
    Param<Addr> trace_addr;
    Param<int> hash_delay;
#if defined(USE_CACHE_IIC)
    SimObjectParam<Repl *> repl;
#endif
    Param<bool> compressed_bus;
    Param<bool> store_compressed;
    Param<bool> adaptive_compression;
    Param<int> compression_latency;
    Param<int> subblock_size;
    Param<Counter> max_miss_count;
    SimObjectParam<HierParams *> hier;
    VectorParam<Range<Addr> > addr_range;
    SimObjectParam<MemTraceWriter *> mem_trace;
    Param<bool> split;
    Param<int> split_size;
    Param<bool> lifo;
    Param<bool> two_queue;
    Param<bool> prefetch_miss;
    Param<bool> prefetch_access;
    Param<int> prefetcher_size;
    Param<bool> prefetch_past_page;
    Param<bool> prefetch_serial_squash;
    Param<Tick> prefetch_latency;
    Param<int> prefetch_degree;
    Param<string> prefetch_policy;
    Param<bool> prefetch_cache_check_push;
    Param<bool> prefetch_use_cpu_id;
    Param<bool> prefetch_data_accesses_only;

END_DECLARE_SIM_OBJECT_PARAMS(BaseCache)


BEGIN_INIT_SIM_OBJECT_PARAMS(BaseCache)

    INIT_PARAM(size, "capacity in bytes"),
    INIT_PARAM(assoc, "associativity"),
    INIT_PARAM(block_size, "block size in bytes"),
    INIT_PARAM(latency, "hit latency in CPU cycles"),
    INIT_PARAM(mshrs, "number of MSHRs (max outstanding requests)"),
    INIT_PARAM(tgts_per_mshr, "max number of accesses per MSHR"),
    INIT_PARAM_DFLT(write_buffers, "number of write buffers", 8),
    INIT_PARAM_DFLT(prioritizeRequests, "always service demand misses first",
		    false),
    INIT_PARAM_DFLT(in_bus, "incoming bus object", NULL),
    INIT_PARAM(out_bus, "outgoing bus object"),
    INIT_PARAM_DFLT(do_copy, "perform fast copies in the cache", false),
    INIT_PARAM_DFLT(protocol, "coherence protocol to use in the cache", NULL),
    INIT_PARAM_DFLT(trace_addr, "address to trace", 0),

    INIT_PARAM_DFLT(hash_delay, "time in cycles of hash access",1),
#if defined(USE_CACHE_IIC)
    INIT_PARAM_DFLT(repl, "replacement policy",NULL),
#endif
    INIT_PARAM_DFLT(compressed_bus,
                    "This cache connects to a compressed memory",
                    false),
    INIT_PARAM_DFLT(store_compressed, "Store compressed data in the cache",
		    false),
    INIT_PARAM_DFLT(adaptive_compression, "Use an adaptive compression scheme",
		    false),
    INIT_PARAM_DFLT(compression_latency,
		    "Latency in cycles of compression algorithm",
		    0),
    INIT_PARAM_DFLT(subblock_size,
		    "Size of subblock in IIC used for compression",
		    0),
    INIT_PARAM_DFLT(max_miss_count,
		    "The number of misses to handle before calling exit",
                    0),
    INIT_PARAM_DFLT(hier,
		    "Hierarchy global variables",
		    &defaultHierParams),
    INIT_PARAM_DFLT(addr_range, "The address range in bytes", 
		    vector<Range<Addr> >(1,RangeIn(0, MaxAddr))),
    INIT_PARAM_DFLT(mem_trace, "Memory trace to write accesses to", NULL),
    INIT_PARAM_DFLT(split, "Whether this is a partitioned cache", false),
    INIT_PARAM_DFLT(split_size, "the number of \"ways\" belonging to the LRU partition", 0),
    INIT_PARAM_DFLT(lifo, "whether you are using a LIFO repl. policy", false),
    INIT_PARAM_DFLT(two_queue, "whether the lifo should have two queue replacement", false),
    INIT_PARAM_DFLT(prefetch_miss, "wheter you are using the hardware prefetcher from Miss stream", false),
    INIT_PARAM_DFLT(prefetch_access, "wheter you are using the hardware prefetcher from Access stream", false),
    INIT_PARAM_DFLT(prefetcher_size, "Number of entries in the harware prefetch queue", 100),
    INIT_PARAM_DFLT(prefetch_past_page, "Allow prefetches to cross virtual page boundaries", false),
    INIT_PARAM_DFLT(prefetch_serial_squash, "Squash prefetches with a later time on a subsequent miss", false),
    INIT_PARAM_DFLT(prefetch_latency, "Latency of the prefetcher", 10),
    INIT_PARAM_DFLT(prefetch_degree, "Degree of the prefetch depth", 1),
    INIT_PARAM_DFLT(prefetch_policy, "Type of prefetcher to use", "none"),
    INIT_PARAM_DFLT(prefetch_cache_check_push, "Check if in cash on push or pop of prefetch queue", true),
    INIT_PARAM_DFLT(prefetch_use_cpu_id, "Use the CPU ID to seperate calculations of prefetches", true),
    INIT_PARAM_DFLT(prefetch_data_accesses_only, "Only prefetch on data not on instruction accesses", false)
END_INIT_SIM_OBJECT_PARAMS(BaseCache)

#define BUILD_CACHE(t, comp, b, c) do {					\
        Prefetcher<CacheTags<t, comp>, b> *pf; \
/*        if (pf_policy == "tagged") {      \
           pf = new   \
                TaggedPrefetcher<CacheTags<t, comp>, b>(prefetcher_size, \
                                                        !prefetch_past_page, \
                                                        prefetch_serial_squash, \
                                                        prefetch_cache_check_push, \
                                                        prefetch_degree,  \
                                                        prefetch_latency); \
        }            \
        else if (pf_policy == "stride") {       \
           pf = new  \
                StridePrefetcher<CacheTags<t, comp>, b>(prefetcher_size, \
                                                        !prefetch_past_page, \