cache.hh

来自「linux下基于c++的处理器仿真平台。具有处理器流水线」· HH 代码 · 共 264 行

/*
 * Copyright (c) 2002, 2003, 2004, 2005
 * The Regents of The University of Michigan
 * All Rights Reserved
 *
 * This code is part of the M5 simulator, developed by Nathan Binkert,
 * Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
 * from Ron Dreslinski, Dave Greene, Lisa Hsu, Kevin Lim, Ali Saidi,
 * and Andrew Schultz.
 *
 * Permission is granted to use, copy, create derivative works and
 * redistribute this software and such derivative works for any
 * purpose, so long as the copyright notice above, this grant of
 * permission, and the disclaimer below appear in all copies made; and
 * so long as the name of The University of Michigan is not used in
 * any advertising or publicity pertaining to the use or distribution
 * of this software without specific, written prior authorization.
 *
 * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
 * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND
 * WITHOUT WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE. THE REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE
 * LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT,
 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM
 * ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN
 * IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH
 * DAMAGES.
 */

/**
 * @file
 * Describes a cache based on template policies.
 */

#ifndef __CACHE_HH__
#define __CACHE_HH__

#include "base/misc.hh" // fatal, panic, and warn
#include "cpu/smt.hh" // SMT_MAX_THREADS

#include "mem/cache/base_cache.hh"
#include "mem/cache/prefetch/prefetcher.hh"

// forward declarations
class Bus;
class ExecContext;

/**
 * A template-policy based cache. The behavior of the cache can be altered by
 * supplying different template policies. TagStore handles all tag and data
 * storage @sa TagStore. Buffering handles all misses and writes/writebacks
 * @sa MissQueue. Coherence handles all coherence policy details @sa
 * UniCoherence, SimpleMultiCoherence.
 */
template <class TagStore, class Buffering, class Coherence>
class Cache : public BaseCache
{
  public:
    /** Define the type of cache block to use. */
    typedef typename TagStore::BlkType BlkType;

    bool prefetchAccess;
  protected:

    /** Tag and data Storage */
    TagStore *tags;
    /** Miss and Writeback handler */
    Buffering *missQueue;
    /** Coherence protocol. */
    Coherence *coherence;

    /** Prefetcher */
    Prefetcher<TagStore, Buffering> *prefetcher;

    /** Do fast copies in this cache. */
    bool doCopy;

    /** Block on a delayed copy. */
    bool blockOnCopy;

    /**
     * The clock ratio of the outgoing bus.
     * Used for calculating critical word first.
     */
    int busRatio;

     /**
      * The bus width in bytes of the outgoing bus.
      * Used for calculating critical word first.
      */
    int busWidth;

     /**
      * A permanent mem req to always be used to cause invalidations.
      * Used to append to target list, to cause an invalidation.
      */
    MemReqPtr invalidateReq;    
    
    /**
     * Temporarily move a block into a MSHR.
     * @todo Remove this when LSQ/SB are fixed and implemented in memtest.
     */
    void pseudoFill(Addr addr, int asid);
    
    /**
     * Temporarily move a block into an existing MSHR.
     * @todo Remove this when LSQ/SB are fixed and implemented in memtest.
     */
    void pseudoFill(MSHR *mshr);

  public:
    
    class Params
    {
      public:
	TagStore *tags;
	Buffering *missQueue; 
	Coherence *coherence;
	bool doCopy;
	bool blockOnCopy;
	BaseCache::Params baseParams;
	Bus *in;
	Bus *out;
	Prefetcher<TagStore, Buffering> *prefetcher;
	bool prefetchAccess;

	Params(TagStore *_tags, Buffering *mq, Coherence *coh,
	       bool do_copy, BaseCache::Params params, Bus * in_bus,
	       Bus * out_bus, Prefetcher<TagStore, Buffering> *_prefetcher,
	       bool prefetch_access) 
	    : tags(_tags), missQueue(mq), coherence(coh), doCopy(do_copy), 
	      blockOnCopy(false), baseParams(params), in(in_bus), out(out_bus),
	      prefetcher(_prefetcher), prefetchAccess(prefetch_access)
	{
	}
    };

    /** Instantiates a basic cache object. */
    Cache(const std::string &_name, HierParams *hier_params, Params &params);

    void regStats();

    /**
     * Performs the access specified by the request.
     * @param req The request to perform.
     * @return The result of the access.
     */
    MemAccessResult access(MemReqPtr &req);

    /**
     * Selects a request to send on the bus.
     * @return The memory request to service.
     */
    MemReqPtr getMemReq();

    /**
     * Was the request was sent successfully?
     * @param req The request.
     * @param success True if the request was sent successfully.
     */
    void sendResult(MemReqPtr &req, bool success);

    /**
     * Handles a response (cache line fill/write ack) from the bus.
     * @param req The request being responded to.
     */
    void handleResponse(MemReqPtr &req);

    /**
     * Start handling a copy transaction.
     * @param req The copy request to perform.
     */
    void startCopy(MemReqPtr &req);

    /**
     * Handle a delayed copy transaction.
     * @param req The delayed copy request to continue.
     * @param addr The address being responded to.
     * @param blk The block of the current response.
     * @param mshr The mshr being handled.
     */
    void handleCopy(MemReqPtr &req, Addr addr, BlkType *blk, MSHR *mshr);

    /**
     * Selects a coherence message to forward to lower levels of the hierarchy.
     * @return The coherence message to forward.
     */
    MemReqPtr getCoherenceReq();

    /**
     * Snoops bus transactions to maintain coherence.
     * @param req The current bus transaction.
     */
    void snoop(MemReqPtr &req);

    void snoopResponse(MemReqPtr &req);

    /**
     * Invalidates the block containing address if found.
     * @param addr The address to look for.
     * @param asid The address space ID of the address.
     * @todo Is this function necessary?
     */
    void invalidateBlk(Addr addr, int asid);

    /**
     * Aquash all requests associated with specified thread.
     * intended for use by I-cache.
     * @param thread_number The thread to squash.
     */
    void squash(int thread_number)
    {
	missQueue->squash(thread_number);
    }

    /**
     * Return the number of outstanding misses in a Cache.
     * Default returns 0.
     *
     * @retval unsigned The number of missing still outstanding.
     */
    unsigned outstandingMisses() const
    {
	return missQueue->getMisses();
    }

    /**
     * Send a response to the slave interface.
     * @param req The request being responded to.
     * @param time The time the response is ready.
     */
    void respond(MemReqPtr &req, Tick time)
    {
	si->respond(req,time);
    }

    /**
     * Perform the access specified in the request and return the estimated
     * time of completion. This function can either update the hierarchy state
     * or just perform the access wherever the data is found depending on the
     * state of the update flag.
     * @param req The memory request to satisfy
     * @param update If true, update the hierarchy, otherwise just perform the
     * request.
     * @return The estimated completion time.
     */
    Tick probe(MemReqPtr &req, bool update);

    /**
     * Snoop for the provided request in the cache and return the estimated
     * time of completion.
     * @todo Can a snoop probe not change state?
     * @param req The memory request to satisfy
     * @param update If true, update the hierarchy, otherwise just perform the
     * request.
     * @return The estimated completion time.
     */
    Tick snoopProbe(MemReqPtr &req, bool update);
};

#endif // __CACHE_HH__