cpu.hh

linux下基于c++的处理器仿真平台。具有处理器流水线

    Stats::Vector<> fetch_choice_dist;
    Stats::Distribution<> fetch_nisn_dist;
    Stats::Distribution<> *fetch_nisn_dist_;

    Stats::Formula idle_rate;
    Stats::Formula branch_rate;
    Stats::Formula fetch_rate;
    Stats::Formula fetch_chance_pct;

    //
    //  Fetch loss counters
    //
    Stats::Vector2d<> stat_floss_icache;
    Stats::Vector2d<> stat_floss_iqfull_deps;
    Stats::Vector2d<> stat_floss_iqfull_fu;
    Stats::Vector2d<> stat_floss_iqfull_dcache;
    Stats::Vector2d<> stat_floss_iqfull_other;
    Stats::Vector2d<> stat_floss_lsqfull_deps;
    Stats::Vector2d<> stat_floss_lsqfull_fu;
    Stats::Vector2d<> stat_floss_lsqfull_other;
    Stats::Vector2d<> stat_floss_lsqfull_dcache;
    Stats::Vector2d<> stat_floss_robfull_dcache;
    Stats::Vector2d<> stat_floss_robfull_fu;
    Stats::Vector2d<> stat_floss_robfull_other;
    Stats::Vector2d<> stat_floss_qfull_other;
    Stats::Vector2d<> stat_floss_other;
    
    std::vector<std::vector<double> > floss_icache;
    std::vector<std::vector<double> > floss_iqfull_deps;
    std::vector<std::vector<double> > floss_iqfull_fu;
    std::vector<std::vector<double> > floss_iqfull_dcache;
    std::vector<std::vector<double> > floss_iqfull_other;
    std::vector<std::vector<double> > floss_lsqfull_deps;
    std::vector<std::vector<double> > floss_lsqfull_fu;
    std::vector<std::vector<double> > floss_lsqfull_other;
    std::vector<std::vector<double> > floss_lsqfull_dcache;
    std::vector<std::vector<double> > floss_robfull_dcache;
    std::vector<std::vector<double> > floss_robfull_fu;
    std::vector<std::vector<double> > floss_robfull_other;
    std::vector<std::vector<double> > floss_qfull_other;
    std::vector<std::vector<double> > floss_other;

    //----------------------------------------------------------------------
    //
    //  Decode/Dispatch
    //

    Stats::Scalar<> secondChoiceCluster;
    Stats::Scalar<> secondChoiceStall;

    Counter used_int_physical_regs[SMT_MAX_THREADS];
    Counter used_fp_physical_regs[SMT_MAX_THREADS];

    Stats::Vector<> reg_int_thrd_occ;
    Stats::Vector<> reg_fp_thrd_occ;
#if 0
    stat_stat_t *chain_create_dist;

    stat_stat_t *inst_class_dist;
#endif
    Stats::Vector<> chain_create_dist;
    Stats::Vector<> inst_class_dist;

    std::vector<uint64_t> dispatch_count;
    Stats::Vector<> dispatch_count_stat;
    Stats::Vector<> dispatched_serializing;
    Stats::Vector<> dispatch_serialize_stall_cycles;
    Stats::Vector<> chain_heads;
    Stats::Formula chain_head_frac;
    Stats::Vector<> chains_insuf;
    Stats::Formula chains_insuf_rate;

    Stats::Vector<> dispatched_ops;
    Stats::Formula dispatched_op_rate;

    Stats::Vector<> rob_cap_events;
    Stats::Vector<> rob_cap_inst_count;
    Stats::Vector<> iq_cap_events;
    Stats::Vector<> iq_cap_inst_count;

    Stats::Formula dispatch_rate;

    Stats::Vector<> mod_n_disp_stalls;
    Stats::Vector<> mod_n_disp_stall_free;
    Stats::Formula mod_n_stall_avg_free;
    Stats::Formula mod_n_stall_frac;

    Stats::Scalar<> reg_int_full;
    Stats::Scalar<> reg_fp_full;

    Stats::Formula reg_int_occ_rate;
    Stats::Formula reg_fp_occ_rate;

    Stats::Scalar<> insufficient_chains;

    Stats::Vector<> two_op_inst_count;
    Stats::Formula two_input_ratio;
    Stats::Vector<> one_rdy_inst_count;
    Stats::Formula one_rdy_ratio;

    //----------------------------------------------------------------------
    //
    //  Issue
    //
    // total number of instructions executed
    Stats::Vector<> exe_inst;
    Stats::Vector<> exe_swp;
    Stats::Vector<> exe_nop;
    Stats::Vector<> exe_refs;
    Stats::Vector<> exe_loads;
    Stats::Vector<> exe_branches;

    Stats::Vector<> issued_ops;

    // total number of loads forwaded from LSQ stores
    Stats::Vector<> lsq_forw_loads;

    // total number of loads ignored due to invalid addresses
    Stats::Vector<> inv_addr_loads;

    // total number of software prefetches ignored due to invalid addresses
    Stats::Vector<> inv_addr_swpfs;

    // total non-speculative bogus addresses seen (debug var)
    Counter sim_invalid_addrs;
    Stats::Vector<> fu_busy;  //cumulative fu busy

    // ready loads blocked due to memory disambiguation
    Stats::Vector<> lsq_blocked_loads;

    Stats::Scalar<> lsqInversion;

    Stats::Vector<> n_issued_dist;
    Stats::VectorDistribution<> issue_delay_dist;

    Stats::VectorDistribution<> queue_res_dist;

    Stats::Vector<> stat_fu_busy;
    Stats::Vector2d<> stat_fuBusy;
    Stats::Vector<> dist_unissued;
    Stats::Vector2d<> stat_issued_inst_type;

    Stats::Formula misspec_cnt;
    Stats::Formula misspec_ipc;
    Stats::Formula issue_rate;
    Stats::Formula issue_stores;
    Stats::Formula issue_op_rate;
    Stats::Formula fu_busy_rate;
    Stats::Formula commit_stores;
    Stats::Formula commit_ipc;
    Stats::Formula commit_ipb;
    Stats::Formula lsq_inv_rate;

    /**
     *These are never registered anywhere, even in old stats package...???
     */
    struct smt_dist_stat_t *dependence_depth_dist;
    struct smt_dist_stat_t *misspec_dependence_depth_dist;

    //----------------------------------------------------------------------
    //
    //  Writeback
    //

    Stats::Vector<> writeback_count;
    Stats::Vector<> producer_inst;
    Stats::Vector<> consumer_inst;
    Stats::Vector<> wb_penalized;

    Stats::Formula wb_rate;
    Stats::Formula wb_fanout;
    Stats::Formula wb_penalized_rate;

    Stats::Distribution<> pred_wb_error_dist;

    //----------------------------------------------------------------------
    //
    //  Commit
    //

    // total number of instructions committed
    Stats::Vector<> stat_com_inst;
    Stats::Vector<> stat_com_swp;
    Stats::Vector<> stat_com_refs;
    Stats::Vector<> stat_com_loads;
    Stats::Vector<> stat_com_membars;
    Stats::Vector<> stat_com_branches;

    std::vector<uint64_t> com_inst;
    std::vector<uint64_t> com_loads;

    virtual Counter totalInstructions() const
    {
	Counter total = 0;
	int size = com_inst.size();
	for (int i = 0; i < size; ++i)
	    total += com_inst[i];
	return total;
    }

    Stats::Distribution<> n_committed_dist;

    Stats::Scalar<> commit_eligible_samples;
    Stats::Vector<> commit_eligible;
    Stats::Formula bw_lim_avg;
    Stats::Formula bw_lim_rate;

    Stats::VectorStandardDeviation<> commit_bwlimit_stat;



    //----------------------------------------------------------------------
    //
    //  Other
    //
    IntervalStats *istat;
    Counter dependence_depth_count;



    ////////////////////////////////////////////////////////////////////////
    //
    //  Methods
    //
    ////////////////////////////////////////////////////////////////////////

  public:
    // main simulation loop (one cycle)
    void tick();

  private:
    class TickEvent : public Event
    {
      private:
	FullCPU *cpu;

      public:
	TickEvent(FullCPU *c)
	    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) { }

	void process() { cpu->tick(); }

	virtual const char *description() { return "tick"; }
    };

    TickEvent tickEvent;

    // PC Sampling Profile
    class PCSampleEvent : public Event
    {
      private:

	FullCPU *cpu;
	int	 interval;

      public:

	PCSampleEvent::PCSampleEvent(int _interval, FullCPU *_cpu);

	~PCSampleEvent() { }

	void process();
    };

    PCSampleEvent *pcSampleEvent;

    m5::hash_map<Addr, Counter> pcSampleHist;

    void dumpPCSampleProfile();

  public:
    void change_thread_state(int thread_number, int activate, int priority);

    virtual void activateContext(int thread_num, int delay);

    //----------------------------------------------------------------------
    //
    //  Caches
    //


    //----------------------------------------------------------------------
    //
    //  Internal Structures
    //
    unsigned IQNumInstructions();
    unsigned IQNumInstructions(unsigned thread);
    unsigned IQNumReadyInstructions();
    unsigned IQNumReadyInstructions(unsigned thread);
    unsigned IQFreeSlots();
    unsigned IQFreeSlotsX(unsigned idx);
    unsigned IQFreeSlots(unsigned thread);
    BaseIQ::iterator IQOldestInstruction();
    BaseIQ::iterator IQOldestInstruction(unsigned thread);
    bool IQCapMet(unsigned thread);

    unsigned IQLeastFull();
    unsigned IQMostFull();

    unsigned IQSize() { return IQNumSlots; }
    BaseIQ::rq_iterator IQIssuableList();

    //  Debugging
    void fuDump();
    void fuDump(int pool);

    void dumpIQ();
    void ROBDump();


    //----------------------------------------------------------------------
    //
    //  Fetch
    //
    void fetch_init();
    void initialize_fetch_list(int);
    void fetch_squash(int thread_number);

    void clear_fetch_stall(Tick when, int thread_number, int stall_type);

    void round_robin_policy(ThreadListElement *thread_list);
    void icount_policy(ThreadListElement *thread_list);


    void fetch();
    void update_icounts();
    void choose_next_thread(ThreadListElement *thread_list);

    // Align an address (typically a PC) to the start of an I-cache block.
    // We fold in the PISA 64- to 32-bit conversion here as well.
    Addr icacheBlockAlignPC(Addr addr)
    {
	addr = TheISA::realPCToFetchPC(addr);
	return (addr & ~((Addr)icache_block_size - 1));
    }

    std::pair<DynInst *, Fault> fetchOneInst(int thread_number);
    std::pair <int, bool> fetchOneLine(int thread_number, int max_to_fetch,
				       int &branch_cnt,
				       bool entering_interrupt);
    int fetchOneThread(int thread_number, int max_to_fetch);

    void instructionFetchComplete(DynInst *inst);

    void fetchRegStats();
    void fetch_dump();



    //----------------------------------------------------------------------
    //
    //  Decode/Dispatch
    //
    void cv_init();
    void cv_init_spec_thread(unsigned thread);

    void dispatch_init();

    void start_decode();
    int choose_decode_thread();
    unsigned choose_dependence_cluster(DynInst *);
    void dispatch();
    enum DispatchEndCause checkThreadForDispatch(unsigned t,
						unsigned idx, unsigned insts);
    enum DispatchEndCause checkGlobalResourcesForDispatch(unsigned insts);

    int choose_iqueue(unsigned thread);
    unsigned dispatch_thread(unsigned thread, unsigned iq_idx, unsigned max,
			     enum DispatchEndCause &cause);
    ROBStation *dispatch_one_inst(DynInst *inst, unsigned iq_idx);


    void fixup_btb_miss(DynInst *inst);

    NewChainInfo choose_chain(DynInst *inst, unsigned clust);
    bool checkClusterForDispatch(unsigned clust, bool chainHead);


    //----------------------------------------------------------------------
    //
    //  Issue
    //
    void lsq_refresh();

    void issue_init();
    void issue();
    bool sb_issue(StoreBuffer::iterator i, unsigned pool_num);
    bool iq_issue(BaseIQ::iterator i, unsigned pool_num);
    bool lsq_issue(BaseIQ::iterator i, unsigned pool_num);
    bool issue_load(BaseIQ::iterator lsq, int *latency);
    bool issue_prefetch(BaseIQ::iterator rs, int *latency);

    void release_fu();

    void update_exe_inst_stats(DynInst *inst);
    bool find_idep_to_blame(BaseIQ::iterator inst, int thread);


    //----------------------------------------------------------------------
    //
    //  Writeback
    //
    void writeback();
    void recover(ROBStation *ROB_branch_entry, int branch_thread);

    void remove_LSQ_element(BaseIQ::iterator);
    void remove_ROB_element(ROBStation *);


    //----------------------------------------------------------------------
    //
    //  Commit
    //
    void commit();
    bool eligible_to_commit(ROBStation *rs,
			    enum CommitEndCause *reason);
    void commit_one_inst(ROBStation *rs);

    unsigned oldest_inst(ROBStation ***clist, unsigned *cnum, unsigned *cx);


    //----------------------------------------------------------------------
    //
    //  Other
    //

    //  Fetch-Loss stuff
    void flossRegStats();
    void flossReset();

    void flossRecord(FlossState *, int num_fetched[]);

    friend struct FlossState;

#if 0
    void blame_fu(int thread, int base_idx, double total_loss,
		  OpClass *fu_classes);
    void blame_commit_stage(FlossState *state,
			    int thread, double total_loss, int base_idx);
    void blame_issue_stage(FlossState *state, int thread,
			   double total_loss, int base_idx);
    void blame_dispatch_stage(FlossState *state, int thread,
			      double loss, int idx);

    void check_counters(FlossState *state);
    Counter total_floss();
#endif

    //  Register stats...
    void dispatchRegStats();
    void issueRegStats();
    void writebackRegStats();
    void commitRegStats();
    void pred_queueRegStats();

    void update_com_inst_stats(DynInst *inst);

    // Register FOrmulas
    void dispatchRegFormulas();
    void fetchRegFormulas();
    void writebackRegFormulas();
    void commitRegFormulas();
    void pred_queueRegFormulas();
    void issueRegFormulas();

    // override of SimObject method: register statistics
    virtual void regStats();
    virtual void regFormulas();

    virtual BranchPred *getBranchPred();
};

/////////////////////////////////////////////////////
//
//   Results from call to choose_chain() use this
//   enum and structure
//
struct NewChainInfo
{
    IQStation::IDEP_info idep_info[TheISA::MaxInstSrcRegs];

    unsigned head_chain;

    int  hm_prediction;
    int  pred_last_op_index;
    int  lr_prediction;

    int  suggested_cluster;

    bool head_of_chain;
    bool out_of_chains;

    //  constructor
    NewChainInfo() {
	out_of_chains = false;
	head_of_chain = false;

	pred_last_op_index = -1;
    }

    std::string str_dump() {
	std::ostringstream s;

	s << "F:";
 	for (int i = 0; i < TheISA::MaxInstSrcRegs; ++i) {
	    if (idep_info[i].chained) {
		s << idep_info[i].follows_chain
		  << ", lat=" << idep_info[i].delay;
	    }
	}
	s << " H:";
	if (head_of_chain)
	    s << head_chain;
	s << std::endl;

	return s.str();
    }

    void dump() {
	std::cout << "New Chain Info:\n";
	std::cout << "   Follows chain(s):\n";

 	for (int i = 0; i < TheISA::MaxInstSrcRegs; ++i) {
	    if (idep_info[i].chained) {
		std::cout << "     chain=" << idep_info[i].follows_chain
		     << ", lat=" << idep_info[i].delay
		     << ", depth=" << idep_info[i].chain_depth << std::endl;
	    }
	}

	if (head_of_chain)
	    std::cout << "   Head of chain: " << head_chain << std::endl;
    }
};
#endif // __ENCUMBERED_CPU_FULL_CPU_HH__