cpu.hh

linux下基于c++的处理器仿真平台。具有处理器流水线

/*
 * Copyright (c) 2001, 2002, 2003, 2004, 2005
 * The Regents of The University of Michigan
 * All Rights Reserved
 *
 * This code is part of the M5 simulator, developed by Nathan Binkert,
 * Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
 * from Ron Dreslinski, Dave Greene, Lisa Hsu, Kevin Lim, Ali Saidi,
 * and Andrew Schultz.
 *
 * Permission is granted to use, copy, create derivative works and
 * redistribute this software and such derivative works for any
 * purpose, so long as the copyright notice above, this grant of
 * permission, and the disclaimer below appear in all copies made; and
 * so long as the name of The University of Michigan is not used in
 * any advertising or publicity pertaining to the use or distribution
 * of this software without specific, written prior authorization.
 *
 * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
 * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND
 * WITHOUT WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE. THE REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE
 * LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT,
 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM
 * ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN
 * IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH
 * DAMAGES.
 */

#ifndef __ENCUMBERED_CPU_FULL_CPU_HH__
#define __ENCUMBERED_CPU_FULL_CPU_HH__

#include <sstream>

#include "base/hashmap.hh"
#include "base/statistics.hh"
#include "base/str.hh"
#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/smt.hh"
#include "encumbered/cpu/full/bpred.hh"
#include "encumbered/cpu/full/fetch.hh"
#include "encumbered/cpu/full/floss_reasons.hh"
#include "encumbered/cpu/full/fu_pool.hh"
#include "encumbered/cpu/full/iq/iq_station.hh"
#include "encumbered/cpu/full/iq/segmented/chain_wire.hh"
#include "encumbered/cpu/full/issue.hh"
#include "encumbered/cpu/full/machine_queue.hh"
#include "encumbered/cpu/full/pipetrace.hh"
#include "encumbered/cpu/full/spec_state.hh"
#include "encumbered/cpu/full/storebuffer.hh"
#include "encumbered/cpu/full/thread.hh"
#include "encumbered/cpu/full/writeback.hh"

class BaseIQ;
class Process;

class DecodeDispatchQueue;
struct IcacheOutputBuffer;
class ROBStation;

struct ClusterSharedInfo;

class IntervalStats;
class MemInterface;

class FullCPU : public BaseCPU
{
  private:

  public:
    ////////////////////////////////////////////
    //
    //  Types...
    //
    ////////////////////////////////////////////
    enum DispatchPolicyEnum {MODULO_N, THREAD_PER_QUEUE, DEPENDENCE};
    enum MemDisambiguationEnum {DISAMBIG_CONSERVATIVE,
				DISAMBIG_NORMAL,
				DISAMBIG_ORACLE};
    enum SoftwarePrefetchPolicy { SWP_ENABLE, SWP_DISABLE, SWP_SQUASH };
    enum CommitModelEnum {
	COMMIT_MODEL_SMT, COMMIT_MODEL_PERTHREAD, COMMIT_MODEL_SSCALAR,
	COMMIT_MODEL_RR
    };

    //typedef CPUTraits<ISATraitsType::ISAType, CPU> CPUTraitsType;

    struct FetchInfo
    {
	unsigned int instructionCount;
	// This is the last fetch we attempted.  We may want to keep a list
	// of addresses, but this is good enough for prefetching.  We
	// did a cache access to this address.
	struct FetchRecord
	{
	    int thread;
	    int asid;
	    Addr addr;
	    MemAccessResult result;

	    FetchRecord(int t, int a, Addr ad, MemAccessResult r)
		: thread(t), asid(a), addr(ad), result(r) { }
	};
	typedef std::vector<FetchRecord> FetchList;
	FetchList fetches;

	FetchInfo() : instructionCount(0) { }

	typedef FetchList::iterator iterator;
	iterator begin() { return(fetches.begin()); }
	iterator end() { return(fetches.end()); }

	void addFetch(int thread, int asid, Addr fetchAddress,
		      MemAccessResult result) {
	    fetches.push_back(FetchRecord(thread, asid, fetchAddress, result));
	}
    };


    enum ChainCreationReason {
	CHAIN_CR_NO_IDEPS=0,       // Inst has no outstanding ideps
	CHAIN_CR_DEPTH,            // Chain has reached max depth
	CHAIN_CR_LOAD,             // Inst is a load
	CHAIN_CR_MULT_IDEPS,       // Chain has multiple ideps
	NUM_CHAIN_CR_CLASSES
    };


    enum HitMissPredFunction {
        HMP_LATENCY = 0, // add latency to load's WB time if predicted miss
        HMP_HEAD_SEL,    // don't mark load as a head if it's predicted to hit
	                 //    and we have less than 25% of chains free
        HMP_BOTH,        // do both of the above...
        NUM_HMP_FUNCS
    };


    ////////////////////////////////////////////
    //
    //  Friends...
    //
    ////////////////////////////////////////////

    Fault execute_instruction(DynInst *fetched_inst, int thread_number);

    ////////////////////////////////////////////
    //
    // Constructor
    //
    ////////////////////////////////////////////

    struct Params : public BaseCPU::Params
    {
    };

    FullCPU(FullCPU::Params *params,
#if FULL_SYSTEM
	    AlphaITB *itb, AlphaDTB *dtb, FunctionalMemory *mem,
#else
	    std::vector<Process *> workload,
#endif // FULL_SYSTEM

	    //
	    // Caches
	    //
	    MemInterface *_icache_interface,
	    MemInterface *_dcache_interface,
	    SoftwarePrefetchPolicy _softwarePrefetchPolicy,

	    //
	    //  Internal Structures
	    //
	    std::vector<BaseIQ *> IQ,
	    unsigned ROB_size,
	    unsigned LSQ_size,
	    unsigned storebuffer_size,


	    //
	    //  Fetch
	    //
	    int fetch_width,
	    int lines_to_fetch,
	    int num_icache_ports,
	    int fetch_branches,
	    int ifq_size,
	    int decode_dispatch_latency,

	    BranchPred *bpred,

	    int fetch_policy,
	    bool fetch_priority_enable,
	    std::vector<unsigned> icount_bias,

	    //
	    //  Decode/Dispatch
	    //
	    bool mt_frontend,
	    int decode_width,
	    int dispatch_to_issue_latency,
	    std::vector<unsigned> _rob_caps,
	    DispatchPolicyEnum disp_policy,
	    bool loose_mod_n_policy,
	    bool use_hm_predictor,
	    bool use_lr_predictor,
	    bool use_lat_predictor,
	    unsigned max_chains,
	    unsigned max_wires,
	    ChainWireInfo::MappingPolicy chainWirePolicy,
	    // hmp_func is hard-coded inside constructor for now...

	    //
	    //  Issue
	    //
	    int issue_width,
	    std::vector<unsigned> _issue_bandwidth,
	    bool inorder_issue,
	    MemDisambiguationEnum disambig_mode,
	    bool prioritized_issue,
	    std::vector<FuncUnitPool *> fupools,

	    std::vector<unsigned> _thread_weights,

	    //
	    // Writeback
	    //
	    int mispred_fixup_penalty,
	    int fault_handler_delay,
	    unsigned iq_comm_latency,

	    //
	    // Commit
	    //
	    int commit_width,
	    bool prioritized_commit,
	    CommitModelEnum commit_model,

	    //
	    //  Other
	    //
	    int _pc_sample_interval,
	    PipeTrace *pt
	);


    ////////////////////////////////////////////
    //
    // Destructor
    //
    ////////////////////////////////////////////
    ~FullCPU();

    void takeOverFrom(BaseCPU *oldCPU);

    // startup callback: initialization after unserialization
    void startup();

    ////////////////////////////////////////////////////////////////////////
    //
    // CONFIGURATION PARAMETERS
    //
    ////////////////////////////////////////////////////////////////////////

    //
    //  Internal Structures
    //
    unsigned ROB_size;
    unsigned LSQ_size;
    unsigned storebuffer_size;

    //
    // Caches
    //
    MemInterface *icacheInterface;
    MemInterface *dcacheInterface;
    SoftwarePrefetchPolicy softwarePrefetchPolicy;

    //
    //  Fetch
    //
    int fetch_width;
    int lines_to_fetch;
    int icache_block_size;
    int insts_per_block;
    int num_icache_ports;
    int fetch_branches;
    int ifq_size;
    int decode_dispatch_latency;

    BranchPred *branch_pred;

    int fetch_policy;
    bool fetch_priority_enable;
    std::vector<unsigned> static_icount_bias;

    //
    //  Decode/Dispatch
    //
    bool mt_frontend;
    int decode_width;
    int dispatch_to_issue_latency;
    DispatchPolicyEnum dispatch_policy;
    std::vector<unsigned> rob_cap;
    bool loose_mod_n_policy;

    // chaining stuff...
    bool use_hm_predictor;
    bool use_lr_predictor;
    bool use_lat_predictor;
    unsigned max_chains;
    unsigned max_wires;
    ChainWireInfo::MappingPolicy chainWirePolicy;
    HitMissPredFunction hmp_func;

    //
    //  Issue
    //
    int issue_width;
    std::vector<unsigned> issue_bandwidth;
    bool inorder_issue;
    MemDisambiguationEnum disambig_mode;
    bool prioritize_issue;
    std::vector<FuncUnitPool *> FUPools;
    std::vector<unsigned> issue_thread_weights;

    //
    //  Writeback
    //
    int mispred_fixup_penalty;
    int fault_handler_delay;
    unsigned iq_comm_latency;

    //
    //  Commit
    //
    int commit_width;
    CommitModelEnum commit_model;
    bool prioritized_commit;

    //
    //  Other
    //
    PipeTrace *ptrace;

    ////////////////////////////////////////////////////////////////////////
    //
    //  Non-parameter Variables (not statistics)
    //
    ////////////////////////////////////////////////////////////////////////

    // Note that this has exactly the same contents as BaseCPU's
    // contexts vector.  However, in this case we know they are
    // SpecExecContext ptrs, so keeping this array around avoids
    // having to cast the members of the contexts vector (which are
    // just plain ExecContext ptrs) when we really need a
    // SpecExecContext ptr.
    SpecExecContext *thread[SMT_MAX_THREADS];

    //----------------------------------------------------------------------
    //
    //  Caches
    //
    MemInterface *itlb;

    MemInterface *dtlb;

    //----------------------------------------------------------------------
    //
    //  Internal Structures
    //
    BaseIQ **IQ;
    BaseIQ *LSQ;
    class MachineQueue<ROBStation> ROB;
    StoreBuffer *storebuffer;

    unsigned numIQueues;  //  ?????
    unsigned IQNumSlots;  //  ?????

    //----------------------------------------------------------------------
    //
    //  Fetch
    //
    unsigned int icache_ports_used_last_fetch;
    InstSeqNum next_fetch_seq;
    int fetch_stall[SMT_MAX_THREADS];
    int fetch_fault_count[SMT_MAX_THREADS];
    enum FetchEndCause fid_cause[SMT_MAX_THREADS];

    // The ifetch queue (ifq) is a queue that buffers fetched
    // instructions until they can enter the decode pipeline.
    FetchQueue ifq[SMT_MAX_THREADS];

    IcacheOutputBuffer *icache_output_buffer[SMT_MAX_THREADS];

    ThreadListElement fetch_list[SMT_MAX_THREADS];
    ThreadInfo thread_info[SMT_MAX_THREADS];

    //----------------------------------------------------------------------
    //
    //  Decode/Dispatch
    //
    unsigned dispatch_width;
    InstSeqNum dispatch_seq;

    DecodeDispatchQueue *decodeQueue;
    unsigned first_decode_thread;
    unsigned dispatch_starting_iqueue[SMT_MAX_THREADS];
    Tick lastDispatchTime[SMT_MAX_THREADS];

    int free_int_physical_regs;
    int free_fp_physical_regs;

    CreateVector create_vector[SMT_MAX_THREADS];
    SpecStateList state_list;

    bool rob_cap_active[SMT_MAX_THREADS];
    bool iq_cap_active[SMT_MAX_THREADS];

    unsigned lastChainUsed;
    class ChainWireInfo *chainWires;

    ClusterSharedInfo *clusterSharedInfo;

    //  Clustering:  which IQ we should use for mod-n instruction placement
    unsigned mod_n_queue_idx;

    //----------------------------------------------------------------------
    //
    //  Issue
    //
    unsigned numFUPools;
    unsigned issue_starting_iqueue;
    unsigned issue_starting_fu_pool;
    unsigned issue_current_fupool_for_sb;

    bool mem_set_this_inst;

    InstSeqNum expected_inorder_seq_num;

    unsigned hp_thread;       // current HP thread
    Tick hp_thread_change;  // when to change HP threads

    unsigned n_issued[SMT_MAX_THREADS];  // currently unused part of fetch-loss
    unsigned n_issued_total;

    struct lsq_store_info_t *store_info[SMT_MAX_THREADS];

    //----------------------------------------------------------------------
    //
    //  Writeback
    //
    EventQueue writebackEventQueue;

    //----------------------------------------------------------------------
    //
    //  Commit
    //

    unsigned n_committed[SMT_MAX_THREADS];  // unused part of fetch-loss
    unsigned n_committed_total;

    Addr commitPC[SMT_MAX_THREADS];	/* Last PC committed */

    unsigned rr_commit_last_thread;

    //----------------------------------------------------------------------
    //
    //  Other
    //

    //  ptrace
    InstSeqNum correctPathSeq[SMT_MAX_THREADS];

    //  fetch-loss
    FlossState floss_state;
    int floss_this_cycle;

    // maximum depth of dependence graph: set after call to
    // update_dependence_depths()
    int max_dependence_depth;

    unsigned chain_heads_in_rob;


    ////////////////////////////////////////////////////////////////////////
    //
    //  Statistics
    //
    ////////////////////////////////////////////////////////////////////////

    //----------------------------------------------------------------------
    //
    //  Internal Structures
    //
    // occupancy counters
    Stats::Scalar<> ROB_fcount;
    Stats::Formula ROB_full_rate;
    Counter lsq_fcount;
    Stats::Scalar<> IFQ_count;	// cumulative IFQ occupancy
    Stats::Formula IFQ_occupancy;
    Stats::Formula IFQ_latency;
    Stats::Vector<> IFQ_fcount; // cumulative IFQ full count
    Stats::Formula IFQ_full_rate;
    Stats::Vector<>  ROB_count;	 // cumulative ROB occupancy
    Stats::Formula ROB_occ_rate;
    Stats::VectorDistribution<> ROB_occ_dist;


    //----------------------------------------------------------------------
    //
    //  Fetch
    //

    Stats::Scalar<> fetch_decisions;
    Stats::Scalar<> fetch_idle_cycles;
    Stats::Scalar<> fetch_idle_icache_blocked_cycles;

    Stats::Vector<> qfull_iq_occupancy;
    Stats::VectorDistribution<> qfull_iq_occ_dist_;
    Stats::Vector<> qfull_rob_occupancy;
    Stats::VectorDistribution<> qfull_rob_occ_dist_;

    // only really useful with ptrace...
    Stats::Scalar<> currentROBCount;

    Stats::Scalar<> conf_predictions;
    Stats::Scalar<> conf_updates;

    Stats::Vector<> priority_changes;

    Stats::Vector<> fetch_chances;
    Stats::Vector<> fetched_inst;
    Stats::Vector<> fetched_branch;