isa_desc

linux下基于c++的处理器仿真平台。具有处理器流水线

#ifdef SS_COMPATIBLE_DISASSEMBLY
	if (_numDestRegs == 0) {
	    printReg(ss, 31);
	    ss << ",";
	}
#endif

	if (_numDestRegs > 0) {
	    printReg(ss, _destRegIdx[0]);
	    ss << ",";
	}

	ccprintf(ss, "(r%d)", RB);

	return ss.str();
    }
}};

def template JumpOrBranchDecode {{
    return (RA == 31)
	? (StaticInst<AlphaISA> *)new %(class_name)s(machInst)
	: (StaticInst<AlphaISA> *)new %(class_name)sAndLink(machInst);
}};

def format CondBranch(code) {{
    code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n';
    iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
			('IsDirectControl', 'IsCondControl'))
    header_output = BasicDeclare.subst(iop)
    decoder_output = BasicConstructor.subst(iop)
    decode_block = BasicDecode.subst(iop)
    exec_output = BasicExecute.subst(iop)
}};

let {{
def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
    # Declare basic control transfer w/o link (i.e. link reg is R31)
    nolink_code = 'NPC = %s;\n' % npc_expr
    nolink_iop = InstObjParams(name, Name, base_class,
                               CodeBlock(nolink_code), flags)
    header_output = BasicDeclare.subst(nolink_iop)
    decoder_output = BasicConstructor.subst(nolink_iop)
    exec_output = BasicExecute.subst(nolink_iop)

    # Generate declaration of '*AndLink' version, append to decls
    link_code = 'Ra = NPC & ~3;\n' + nolink_code
    link_iop = InstObjParams(name, Name + 'AndLink', base_class,
                             CodeBlock(link_code), flags)
    header_output += BasicDeclare.subst(link_iop)
    decoder_output += BasicConstructor.subst(link_iop)
    exec_output += BasicExecute.subst(link_iop)

    # need to use link_iop for the decode template since it is expecting
    # the shorter version of class_name (w/o "AndLink")

    return (header_output, decoder_output,
            JumpOrBranchDecode.subst(nolink_iop), exec_output)
}};

def format UncondBranch(*flags) {{
    flags += ('IsUncondControl', 'IsDirectControl')
    (header_output, decoder_output, decode_block, exec_output) = \
        UncondCtrlBase(name, Name, 'Branch', 'NPC + disp', flags)
}};

def format Jump(*flags) {{
    flags += ('IsUncondControl', 'IsIndirectControl')
    (header_output, decoder_output, decode_block, exec_output) = \
        UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (NPC & 1)', flags)
}};


////////////////////////////////////////////////////////////////////
//
// PAL calls
//

output header {{
    /**
     * Base class for emulated call_pal calls (used only in
     * non-full-system mode).
     */
    class EmulatedCallPal : public AlphaStaticInst
    {
      protected:

	/// Constructor.
	EmulatedCallPal(const char *mnem, MachInst _machInst,
			OpClass __opClass)
	    : AlphaStaticInst(mnem, _machInst, __opClass)
	{
	}

	std::string
	generateDisassembly(Addr pc, const SymbolTable *symtab) const;
    };
}};

output decoder {{
    std::string
    EmulatedCallPal::generateDisassembly(Addr pc,
					 const SymbolTable *symtab) const
    {
#ifdef SS_COMPATIBLE_DISASSEMBLY
	return csprintf("%s %s", "call_pal", mnemonic);
#else
	return csprintf("%-10s %s", "call_pal", mnemonic);
#endif
    }
}};

def format EmulatedCallPal(code, *flags) {{
    iop = InstObjParams(name, Name, 'EmulatedCallPal', CodeBlock(code), flags)
    header_output = BasicDeclare.subst(iop)
    decoder_output = BasicConstructor.subst(iop)
    decode_block = BasicDecode.subst(iop)
    exec_output = BasicExecute.subst(iop)
}};

output header {{
    /**
     * Base class for full-system-mode call_pal instructions.
     * Probably could turn this into a leaf class and get rid of the
     * parser template.
     */
    class CallPalBase : public AlphaStaticInst
    {
      protected:
	int palFunc;	///< Function code part of instruction
	int palOffset;	///< Target PC, offset from IPR_PAL_BASE
	bool palValid;	///< is the function code valid?
	bool palPriv;	///< is this call privileged?

	/// Constructor.
	CallPalBase(const char *mnem, MachInst _machInst,
		    OpClass __opClass);

	std::string
	generateDisassembly(Addr pc, const SymbolTable *symtab) const;
    };
}};

output decoder {{
    inline
    CallPalBase::CallPalBase(const char *mnem, MachInst _machInst,
			     OpClass __opClass)
	: AlphaStaticInst(mnem, _machInst, __opClass),
	palFunc(PALFUNC)
    {
	// From the 21164 HRM (paraphrased):
	// Bit 7 of the function code (mask 0x80) indicates
	// whether the call is privileged (bit 7 == 0) or
	// unprivileged (bit 7 == 1).  The privileged call table
	// starts at 0x2000, the unprivielged call table starts at
	// 0x3000.  Bits 5-0 (mask 0x3f) are used to calculate the
	// offset.
	const int palPrivMask = 0x80;
	const int palOffsetMask = 0x3f;

	// Pal call is invalid unless all other bits are 0
	palValid = ((machInst & ~(palPrivMask | palOffsetMask)) == 0);
	palPriv = ((machInst & palPrivMask) == 0);
	int shortPalFunc = (machInst & palOffsetMask);
	// Add 1 to base to set pal-mode bit
	palOffset = (palPriv ? 0x2001 : 0x3001) + (shortPalFunc << 6);
    }

    std::string
    CallPalBase::generateDisassembly(Addr pc, const SymbolTable *symtab) const
    {
	return csprintf("%-10s %#x", "call_pal", palFunc);
    }
}};

def format CallPal(code, *flags) {{
    iop = InstObjParams(name, Name, 'CallPalBase', CodeBlock(code), flags)
    header_output = BasicDeclare.subst(iop)
    decoder_output = BasicConstructor.subst(iop)
    decode_block = BasicDecode.subst(iop)
    exec_output = BasicExecute.subst(iop)
}};

////////////////////////////////////////////////////////////////////
//
// hw_ld, hw_st
//

output header {{
    /**
     * Base class for hw_ld and hw_st.
     */
    class HwLoadStore : public Memory
    {
      protected:

	/// Displacement for EA calculation (signed).
	int16_t disp;

	/// Constructor
	HwLoadStore(const char *mnem, MachInst _machInst, OpClass __opClass,
		    StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
		    StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr);

	std::string
	generateDisassembly(Addr pc, const SymbolTable *symtab) const;
    };
}};


output decoder {{
    inline
    HwLoadStore::HwLoadStore(const char *mnem, MachInst _machInst,
			     OpClass __opClass,
			     StaticInstPtr<AlphaISA> _eaCompPtr,
			     StaticInstPtr<AlphaISA> _memAccPtr)
	: Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
	disp(HW_LDST_DISP)
    {
	memAccessFlags = 0;
	if (HW_LDST_PHYS) memAccessFlags |= PHYSICAL;
	if (HW_LDST_ALT)  memAccessFlags |= ALTMODE;
	if (HW_LDST_VPTE) memAccessFlags |= VPTE;
	if (HW_LDST_LOCK) memAccessFlags |= LOCKED;
    }

    std::string
    HwLoadStore::generateDisassembly(Addr pc, const SymbolTable *symtab) const
    {
#ifdef SS_COMPATIBLE_DISASSEMBLY
	return csprintf("%-10s r%d,%d(r%d)", mnemonic, RA, disp, RB);
#else
	// HW_LDST_LOCK and HW_LDST_COND are the same bit.
	const char *lock_str =
	    (HW_LDST_LOCK) ? (flags[IsLoad] ? ",LOCK" : ",COND") : "";

	return csprintf("%-10s r%d,%d(r%d)%s%s%s%s%s",
			mnemonic, RA, disp, RB,
			HW_LDST_PHYS ? ",PHYS" : "",
			HW_LDST_ALT ? ",ALT" : "",
			HW_LDST_QUAD ? ",QUAD" : "",
			HW_LDST_VPTE ? ",VPTE" : "",
			lock_str);
#endif
    }
}};

def format HwLoadStore(ea_code, memacc_code, class_ext, *flags) {{
    (header_output, decoder_output, decode_block, exec_output) = \
        LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
		      flags = flags, base_class = 'HwLoadStore')
}};


def format HwStoreCond(ea_code, memacc_code, postacc_code, class_ext, *flags) {{
    (header_output, decoder_output, decode_block, exec_output) = \
        LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
		      postacc_code, flags = flags, base_class = 'HwLoadStore')
}};


output header {{
    /**
     * Base class for hw_mfpr and hw_mtpr.
     */
    class HwMoveIPR : public AlphaStaticInst
    {
      protected:
	/// Index of internal processor register.
	int ipr_index;

	/// Constructor
	HwMoveIPR(const char *mnem, MachInst _machInst, OpClass __opClass)
	    : AlphaStaticInst(mnem, _machInst, __opClass),
	      ipr_index(HW_IPR_IDX)
	{
	}

	std::string
	generateDisassembly(Addr pc, const SymbolTable *symtab) const;
    };
}};

output decoder {{
    std::string
    HwMoveIPR::generateDisassembly(Addr pc, const SymbolTable *symtab) const
    {
	if (_numSrcRegs > 0) {
	    // must be mtpr
	    return csprintf("%-10s r%d,IPR(%#x)",
			    mnemonic, RA, ipr_index);
	}
	else {
	    // must be mfpr
	    return csprintf("%-10s IPR(%#x),r%d",
			    mnemonic, ipr_index, RA);
	}
    }
}};

def format HwMoveIPR(code) {{
    iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code),
			['IprAccessOp'])
    header_output = BasicDeclare.subst(iop)
    decoder_output = BasicConstructor.subst(iop)
    decode_block = BasicDecode.subst(iop)
    exec_output = BasicExecute.subst(iop)
}};


////////////////////////////////////////////////////////////////////
//
// Unimplemented instructions
//

output header {{
    /**
     * Static instruction class for unimplemented instructions that
     * cause simulator termination.  Note that these are recognized
     * (legal) instructions that the simulator does not support; the
     * 'Unknown' class is used for unrecognized/illegal instructions.
     * This is a leaf class.
     */
    class FailUnimplemented : public AlphaStaticInst
    {
      public:
	/// Constructor
	FailUnimplemented(const char *_mnemonic, MachInst _machInst)
	    : AlphaStaticInst(_mnemonic, _machInst, No_OpClass)
	{
	    // don't call execute() (which panics) if we're on a
	    // speculative path
	    flags[IsNonSpeculative] = true;
	}

	%(BasicExecDeclare)s

	std::string
	generateDisassembly(Addr pc, const SymbolTable *symtab) const;
    };

    /**
     * Base class for unimplemented instructions that cause a warning
     * to be printed (but do not terminate simulation).  This
     * implementation is a little screwy in that it will print a
     * warning for each instance of a particular unimplemented machine
     * instruction, not just for each unimplemented opcode.  Should
     * probably make the 'warned' flag a static member of the derived
     * class.
     */
    class WarnUnimplemented : public AlphaStaticInst
    {
      private:
	/// Have we warned on this instruction yet?
	mutable bool warned;

      public:
	/// Constructor
	WarnUnimplemented(const char *_mnemonic, MachInst _machInst)
	    : AlphaStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
	{
	    // don't call execute() (which panics) if we're on a
	    // speculative path
	    flags[IsNonSpeculative] = true;
	}

	%(BasicExecDeclare)s

	std::string
	generateDisassembly(Addr pc, const SymbolTable *symtab) const;
    };
}};

output decoder {{
    std::string
    FailUnimplemented::generateDisassembly(Addr pc,
					   const SymbolTable *symtab) const
    {
	return csprintf("%-10s (unimplemented)", mnemonic);
    }

    std::string
    WarnUnimplemented::generateDisassembly(Addr pc,
					   const SymbolTable *symtab) const
    {
#ifdef SS_COMPATIBLE_DISASSEMBLY
	return csprintf("%-10s", mnemonic);
#else
	return csprintf("%-10s (unimplemented)", mnemonic);
#endif
    }
}};

output exec {{
    Fault
    FailUnimplemented::execute(%(CPU_exec_context)s *xc,
			       Trace::InstRecord *traceData) const
    {
	panic("attempt to execute unimplemented instruction '%s' "
	      "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
	return Unimplemented_Opcode_Fault;
    }

    Fault
    WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
			       Trace::InstRecord *traceData) const
    {
	if (!warned) {
	    warn("instruction '%s' unimplemented\n", mnemonic);
	    warned = true;
	}

	return No_Fault;
    }
}};


def format FailUnimpl() {{
    iop = InstObjParams(name, 'FailUnimplemented')
    decode_block = BasicDecodeWithMnemonic.subst(iop)
}};

def format WarnUnimpl() {{
    iop = InstObjParams(name, 'WarnUnimplemented')
    decode_block = BasicDecodeWithMnemonic.subst(iop)
}};

output header {{
    /**
     * Static instruction class for unknown (illegal) instructions.
     * These cause simulator termination if they are executed in a
     * non-speculative mode.  This is a leaf class.
     */
    class Unknown : public AlphaStaticInst
    {
      public:
	/// Constructor
	Unknown(MachInst _machInst)
	    : AlphaStaticInst("unknown", _machInst, No_OpClass)
	{
	    // don't call execute() (which panics) if we're on a
	    // speculative path
	    flags[IsNonSpeculative] = true;
	}

	%(BasicExecDeclare)s

	std::string
	generateDisassembly(Addr pc, const SymbolTable *symtab) const;
    };
}};

////////////////////////////////////////////////////////////////////
//
// Unknown instructions
//

output decoder {{
    std::string
    Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
    {
	return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
			"unknown", machInst, OPCODE);
    }
}};