📄 m5stats.txt
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62 0 64 0 66 0 68 0 70 0 72 0 74 0 76 0 78 0 80 0 82 0 84 0 86 0 88 0 90 0 92 0 94 0 96 0 98 0 cpu.IQ:residence:(null).max_value 0 cpu.IQ:residence:(null).end_distcpu.IQ:residence:IntAlu.start_dist # cycles from dispatch to issuecpu.IQ:residence:IntAlu.samples 867818 cpu.IQ:residence:IntAlu.min_value 1 0 153516 1768.99% 1768.99% 2 126547 1458.22% 3227.21% 4 68428 788.51% 4015.72% 6 93011 1071.78% 5087.50% 8 70652 814.13% 5901.63% 10 63744 734.53% 6636.16% 12 72111 830.95% 7467.11% 14 45048 519.10% 7986.20% 16 35367 407.54% 8393.74% 18 41414 477.22% 8870.96% 20 26883 309.78% 9180.74% 22 13978 161.07% 9341.81% 24 9556 110.12% 9451.92% 26 8171 94.16% 9546.08% 28 5036 58.03% 9604.11% 30 4824 55.59% 9659.70% 32 2476 28.53% 9688.23% 34 2009 23.15% 9711.38% 36 1895 21.84% 9733.22% 38 1055 12.16% 9745.37% 40 825 9.51% 9754.88% 42 486 5.60% 9760.48% 44 312 3.60% 9764.07% 46 205 2.36% 9766.44% 48 95 1.09% 9767.53% 50 77 0.89% 9768.42% 52 97 1.12% 9769.54% 54 99 1.14% 9770.68% 56 127 1.46% 9772.14% 58 153 1.76% 9773.90% 60 210 2.42% 9776.32% 62 106 1.22% 9777.55% 64 158 1.82% 9779.37% 66 144 1.66% 9781.03% 68 108 1.24% 9782.27% 70 109 1.26% 9783.53% 72 104 1.20% 9784.72% 74 75 0.86% 9785.59% 76 76 0.88% 9786.46% 78 85 0.98% 9787.44% 80 117 1.35% 9788.79% 82 101 1.16% 9789.96% 84 123 1.42% 9791.37% 86 118 1.36% 9792.73% 88 70 0.81% 9793.54% 90 90 1.04% 9794.58% 92 189 2.18% 9796.75% 94 153 1.76% 9798.52% 96 108 1.24% 9799.76% 98 158 1.82% 9801.58%cpu.IQ:residence:IntAlu.overflows 17219 cpu.IQ:residence:IntAlu.max_value 804 cpu.IQ:residence:IntAlu.end_distcpu.IQ:residence:IntMult.start_dist # cycles from dispatch to issuecpu.IQ:residence:IntMult.samples 313 cpu.IQ:residence:IntMult.min_value 1 0 9 287.54% 287.54% 2 31 990.42% 1277.96% 4 8 255.59% 1533.55% 6 115 3674.12% 5207.67% 8 7 223.64% 5431.31% 10 17 543.13% 5974.44% 12 17 543.13% 6517.57% 14 15 479.23% 6996.81% 16 11 351.44% 7348.24% 18 23 734.82% 8083.07% 20 3 95.85% 8178.91% 22 6 191.69% 8370.61% 24 3 95.85% 8466.45% 26 6 191.69% 8658.15% 28 2 63.90% 8722.04% 30 0 0.00% 8722.04% 32 0 0.00% 8722.04% 34 4 127.80% 8849.84% 36 0 0.00% 8849.84% 38 4 127.80% 8977.64% 40 0 0.00% 8977.64% 42 5 159.74% 9137.38% 44 0 0.00% 9137.38% 46 0 0.00% 9137.38% 48 0 0.00% 9137.38% 50 0 0.00% 9137.38% 52 1 31.95% 9169.33% 54 0 0.00% 9169.33% 56 0 0.00% 9169.33% 58 0 0.00% 9169.33% 60 0 0.00% 9169.33% 62 0 0.00% 9169.33% 64 0 0.00% 9169.33% 66 0 0.00% 9169.33% 68 0 0.00% 9169.33% 70 0 0.00% 9169.33% 72 1 31.95% 9201.28% 74 0 0.00% 9201.28% 76 0 0.00% 9201.28% 78 0 0.00% 9201.28% 80 0 0.00% 9201.28% 82 0 0.00% 9201.28% 84 1 31.95% 9233.23% 86 0 0.00% 9233.23% 88 0 0.00% 9233.23% 90 0 0.00% 9233.23% 92 0 0.00% 9233.23% 94 0 0.00% 9233.23% 96 0 0.00% 9233.23% 98 1 31.95% 9265.18%cpu.IQ:residence:IntMult.overflows 23 cpu.IQ:residence:IntMult.max_value 157 cpu.IQ:residence:IntMult.end_distcpu.IQ:residence:IntDiv.start_dist # cycles from dispatch to issuecpu.IQ:residence:IntDiv.samples 0 cpu.IQ:residence:IntDiv.min_value 0 0 0 2 0 4 0 6 0 8 0 10 0 12 0 14 0 16 0 18 0 20 0 22 0 24 0 26 0 28 0 30 0 32 0 34 0 36 0 38 0 40 0 42 0 44 0 46 0 48 0 50 0 52 0 54 0 56 0 58 0 60 0 62 0 64 0 66 0 68 0 70 0 72 0 74 0 76 0 78 0 80 0 82 0 84 0 86 0 88 0 90 0 92 0 94 0 ⌨️ 快捷键说明
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