📄 m5stats.txt
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62 0 64 0 66 0 68 0 70 0 72 0 74 0 76 0 78 0 80 0 82 0 84 0 86 0 88 0 90 0 92 0 94 0 96 0 98 0 cpu.IQ:residence:(null).max_value 0 cpu.IQ:residence:(null).end_distcpu.IQ:residence:IntAlu.start_dist # cycles from dispatch to issuecpu.IQ:residence:IntAlu.samples 343954 cpu.IQ:residence:IntAlu.min_value 1 0 38039 1105.93% 1105.93% 2 22458 652.94% 1758.87% 4 17272 502.16% 2261.03% 6 28283 822.29% 3083.32% 8 19915 579.00% 3662.32% 10 19342 562.34% 4224.66% 12 31084 903.73% 5128.39% 14 21166 615.37% 5743.76% 16 23136 672.65% 6416.41% 18 27610 802.72% 7219.13% 20 17620 512.28% 7731.41% 22 5441 158.19% 7889.60% 24 7592 220.73% 8110.33% 26 3480 101.18% 8211.51% 28 4153 120.74% 8332.25% 30 2268 65.94% 8398.19% 32 7231 210.23% 8608.42% 34 9437 274.37% 8882.79% 36 5186 150.78% 9033.56% 38 3933 114.35% 9147.91% 40 6872 199.79% 9347.70% 42 5074 147.52% 9495.22% 44 3297 95.86% 9591.08% 46 5600 162.81% 9753.89% 48 2432 70.71% 9824.60% 50 432 12.56% 9837.16% 52 1181 34.34% 9871.49% 54 11 0.32% 9871.81% 56 11 0.32% 9872.13% 58 5 0.15% 9872.28% 60 4 0.12% 9872.40% 62 13 0.38% 9872.77% 64 63 1.83% 9874.61% 66 3 0.09% 9874.69% 68 4 0.12% 9874.81% 70 0 0.00% 9874.81% 72 0 0.00% 9874.81% 74 0 0.00% 9874.81% 76 0 0.00% 9874.81% 78 0 0.00% 9874.81% 80 3 0.09% 9874.90% 82 7 0.20% 9875.10% 84 15 0.44% 9875.54% 86 19 0.55% 9876.09% 88 16 0.47% 9876.55% 90 31 0.90% 9877.45% 92 44 1.28% 9878.73% 94 43 1.25% 9879.98% 96 64 1.86% 9881.84% 98 42 1.22% 9883.07%cpu.IQ:residence:IntAlu.overflows 4022 cpu.IQ:residence:IntAlu.max_value 312 cpu.IQ:residence:IntAlu.end_distcpu.IQ:residence:IntMult.start_dist # cycles from dispatch to issuecpu.IQ:residence:IntMult.samples 10 cpu.IQ:residence:IntMult.min_value 2 0 0 0.00% 0.00% 2 1 1000.00% 1000.00% 4 0 0.00% 1000.00% 6 3 3000.00% 4000.00% 8 0 0.00% 4000.00% 10 0 0.00% 4000.00% 12 1 1000.00% 5000.00% 14 1 1000.00% 6000.00% 16 0 0.00% 6000.00% 18 1 1000.00% 7000.00% 20 0 0.00% 7000.00% 22 0 0.00% 7000.00% 24 0 0.00% 7000.00% 26 0 0.00% 7000.00% 28 0 0.00% 7000.00% 30 0 0.00% 7000.00% 32 0 0.00% 7000.00% 34 0 0.00% 7000.00% 36 0 0.00% 7000.00% 38 0 0.00% 7000.00% 40 0 0.00% 7000.00% 42 0 0.00% 7000.00% 44 0 0.00% 7000.00% 46 0 0.00% 7000.00% 48 0 0.00% 7000.00% 50 0 0.00% 7000.00% 52 0 0.00% 7000.00% 54 0 0.00% 7000.00% 56 0 0.00% 7000.00% 58 0 0.00% 7000.00% 60 0 0.00% 7000.00% 62 0 0.00% 7000.00% 64 0 0.00% 7000.00% 66 0 0.00% 7000.00% 68 0 0.00% 7000.00% 70 0 0.00% 7000.00% 72 0 0.00% 7000.00% 74 0 0.00% 7000.00% 76 0 0.00% 7000.00% 78 0 0.00% 7000.00% 80 0 0.00% 7000.00% 82 0 0.00% 7000.00% 84 0 0.00% 7000.00% 86 0 0.00% 7000.00% 88 0 0.00% 7000.00% 90 0 0.00% 7000.00% 92 0 0.00% 7000.00% 94 0 0.00% 7000.00% 96 0 0.00% 7000.00% 98 0 0.00% 7000.00%cpu.IQ:residence:IntMult.overflows 3 cpu.IQ:residence:IntMult.max_value 141 cpu.IQ:residence:IntMult.end_distcpu.IQ:residence:IntDiv.start_dist # cycles from dispatch to issuecpu.IQ:residence:IntDiv.samples 0 cpu.IQ:residence:IntDiv.min_value 0 0 0 2 0 4 0 6 0 8 0 10 0 12 0 14 0 16 0 18 0 20 0 22 0 24 0 26 0 28 0 30 0 32 0 34 0 36 0 38 0 40 0 42 0 44 0 46 0 48 0 50 0 52 0 54 0 56 0 58 0 60 0 62 0 64 0 66 0 68 0 70 0 72 0 74 0 76 0 78 0 80 0 82 0 84 0 86 0 88 0 90 0 92 0 94 0 ⌨️ 快捷键说明
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