📄 m5stats.txt
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cpu.FETCH:rate_dist_0.samples 331035 cpu.FETCH:rate_dist_0.min_value 0 0 673 20.33% 1 15903 480.40% 2 16062 485.21% 3 19139 578.16% 4 14532 438.99% 5 17755 536.35% 6 50254 1518.09% 7 6523 197.05% 8 190194 5745.43% cpu.FETCH:rate_dist_0.max_value 8 cpu.FETCH:rate_dist_0.end_distcpu.FETCH:rate_dist_1.start_dist # Number of instructions fetched each cycle (Thread 1)cpu.FETCH:rate_dist_1.samples 135961 cpu.FETCH:rate_dist_1.min_value 0 0 1270 93.41% 1 1474 108.41% 2 1164 85.61% 3 1130 83.11% 4 1727 127.02% 5 1453 106.87% 6 2989 219.84% 7 3037 223.37% 8 121717 8952.35% cpu.FETCH:rate_dist_1.max_value 8 cpu.FETCH:rate_dist_1.end_distcpu.IFQ:count 19989497 # cumulative IFQ occupancycpu.IFQ:full_count 422698 # cumulative IFQ full countcpu.IFQ:full_count_0 289153 # cumulative IFQ full countcpu.IFQ:full_count_1 133545 # cumulative IFQ full countcpu.IFQ:full_rate 68.717415 # fraction of time (cycle's) IFQ was fullcpu.IFQ:full_rate_0 47.007194 # fraction of time (cycle's) IFQ was fullcpu.IFQ:full_rate_1 21.710221 # fraction of time (cycle's) IFQ was fullcpu.IFQ:latency 10.021370 # avg IFQ occupant latency (cycle's)cpu.IFQ:latency_0 13.942905 # avg IFQ occupant latency (cycle's)cpu.IFQ:latency_1 35.630695 # avg IFQ occupant latency (cycle's)cpu.IFQ:occupancy 32.496642 # avg IFQ occupancy (inst's)cpu.IFQ:qfull_iq_occ 17185552 # Number of insts in IQ when fetch-queue fullcpu.IFQ:qfull_iq_occ_0 8094601 # Number of insts in IQ when fetch-queue fullcpu.IFQ:qfull_iq_occ_1 9090951 # Number of insts in IQ when fetch-queue fullcpu.IFQ:qfull_iq_occ_dist_0.start_dist # Number of insts in IQ when fetch-queue fullcpu.IFQ:qfull_iq_occ_dist_0.samples 288048 cpu.IFQ:qfull_iq_occ_dist_0.min_value 0 0 124226 4312.68% 10 19327 670.96% 20 12940 449.23% 30 23092 801.67% 40 13891 482.25% 50 22639 785.95% 60 71933 2497.26% cpu.IFQ:qfull_iq_occ_dist_0.max_value 64 cpu.IFQ:qfull_iq_occ_dist_0.end_distcpu.IFQ:qfull_iq_occ_dist_1.start_dist # Number of insts in IQ when fetch-queue fullcpu.IFQ:qfull_iq_occ_dist_1.samples 288048 cpu.IFQ:qfull_iq_occ_dist_1.min_value 0 0 114808 3985.72% 10 11667 405.04% 20 8872 308.00% 30 19629 681.45% 40 13128 455.76% 50 35833 1243.99% 60 84111 2920.03% cpu.IFQ:qfull_iq_occ_dist_1.max_value 64 cpu.IFQ:qfull_iq_occ_dist_1.end_distcpu.IFQ:qfull_rob_occ 28414982 # Number of insts in ROB when fetch-queue fullcpu.IFQ:qfull_rob_occ_0 14930509 # Number of insts in ROB when fetch-queue fullcpu.IFQ:qfull_rob_occ_1 13484473 # Number of insts in ROB when fetch-queue fullcpu.IFQ:qfull_rob_occ_dist_0.start_dist # Number of insts in ROB when fetch-queue fullcpu.IFQ:qfull_rob_occ_dist_0.samples 288048 cpu.IFQ:qfull_rob_occ_dist_0.min_value 0 0 94390 3276.88% 10 9437 327.62% 20 17198 597.05% 30 12576 436.59% 40 15228 528.66% 50 15193 527.45% 60 9612 333.69% 70 16381 568.69% 80 21919 760.95% 90 17906 621.63% 100 12377 429.69% 110 37499 1301.83% 120 1137 39.47% 130 652 22.64% 140 369 12.81% 150 587 20.38% 160 322 11.18% 170 292 10.14% 180 950 32.98% 190 4023 139.66% 200 0 0.00% cpu.IFQ:qfull_rob_occ_dist_0.max_value 196 cpu.IFQ:qfull_rob_occ_dist_0.end_distcpu.IFQ:qfull_rob_occ_dist_1.start_dist # Number of insts in ROB when fetch-queue fullcpu.IFQ:qfull_rob_occ_dist_1.samples 288048 cpu.IFQ:qfull_rob_occ_dist_1.min_value 0 0 93761 3255.05% 10 9177 318.59% 20 6714 233.09% 30 7466 259.19% 40 11825 410.52% 50 15847 550.15% 60 36313 1260.66% 70 88175 3061.12% 80 4741 164.59% 90 1860 64.57% 100 1777 61.69% 110 1090 37.84% 120 1961 68.08% 130 619 21.49% 140 1134 39.37% 150 1227 42.60% 160 1097 38.08% 170 616 21.39% 180 604 20.97% 190 2044 70.96% 200 0 0.00% cpu.IFQ:qfull_rob_occ_dist_1.max_value 196 cpu.IFQ:qfull_rob_occ_dist_1.end_distcpu.IQ:cap_events 0 # number of cycles where IQ cap was activecpu.IQ:cap_events_0 0 # number of cycles where IQ cap was activecpu.IQ:cap_events_1 0 # number of cycles where IQ cap was activecpu.IQ:cap_inst 0 # number of instructions held up by IQ capcpu.IQ:cap_inst_0 0 # number of instructions held up by IQ capcpu.IQ:cap_inst_1 0 # number of instructions held up by IQ capcpu.IQ:residence:(null).start_dist # cycles from dispatch to issuecpu.IQ:residence:(null).samples 0 cpu.IQ:residence:(null).min_value 0 0 0 2 0 4 0 6 0 8 0 10 0 12 0 14 0 16 0 18 0 20 0 22 0 24 0 26 0 28 0 30 0 32 0 34 0 36 0 38 0 40 0 42 0 44 0 46 0 48 0 50 0 52 0 54 0 56 0 58 0 60 0 62 0 64 0 66 0 68 0 70 0 72 0 74 0 76 0
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