📄 m5stats.txt
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---------- Begin Simulation Statistics ----------cpu.COM:IPB 6.214547 # Committed instructions per branchcpu.COM:IPB_0 6.199268 # Committed instructions per branchcpu.COM:IPB_1 6.198540 # Committed instructions per branchcpu.COM:IPB_2 6.252234 # Committed instructions per branchcpu.COM:IPB_3 6.204270 # Committed instructions per branchcpu.COM:IPC 2.083710 # Committed instructions per cyclecpu.COM:IPC_0 0.504032 # Committed instructions per cyclecpu.COM:IPC_1 0.503763 # Committed instructions per cyclecpu.COM:IPC_2 0.562903 # Committed instructions per cyclecpu.COM:IPC_3 0.513012 # Committed instructions per cyclecpu.COM:branches 595655 # Number of branches committedcpu.COM:branches_0 144439 # Number of branches committedcpu.COM:branches_1 144379 # Number of branches committedcpu.COM:branches_2 159943 # Number of branches committedcpu.COM:branches_3 146894 # Number of branches committedcpu.COM:bw_lim_avg 22.8013 # Avg number not committed in cycles BW limitedcpu.COM:bw_lim_avg_0 5.0727 # Avg number not committed in cycles BW limitedcpu.COM:bw_lim_avg_1 5.0811 # Avg number not committed in cycles BW limitedcpu.COM:bw_lim_avg_2 7.1676 # Avg number not committed in cycles BW limitedcpu.COM:bw_lim_avg_3 5.4799 # Avg number not committed in cycles BW limitedcpu.COM:bw_lim_events 165901 # number cycles where commit BW limit reachedcpu.COM:bw_lim_rate 2.1293 # Average number not committed due to BW (over all cycles)cpu.COM:bw_lim_rate_0 0.4737 # Average number not committed due to BW (over all cycles)cpu.COM:bw_lim_rate_1 0.4745 # Average number not committed due to BW (over all cycles)cpu.COM:bw_lim_rate_2 0.6694 # Average number not committed due to BW (over all cycles)cpu.COM:bw_lim_rate_3 0.5117 # Average number not committed due to BW (over all cycles)cpu.COM:bw_lim_stdev_0_mean 5.0727 # standard deviation of bw_lim_avg valuecpu.COM:bw_lim_stdev_0_stdev 12.2792 # standard deviation of bw_lim_avg value**Ignore: cpu.COM:bw_lim_stdev_0_TOT 165901.0000 # standard deviation of bw_lim_avg valuecpu.COM:bw_lim_stdev_1_mean 5.0811 # standard deviation of bw_lim_avg valuecpu.COM:bw_lim_stdev_1_stdev 12.3074 # standard deviation of bw_lim_avg value**Ignore: cpu.COM:bw_lim_stdev_1_TOT 165901.0000 # standard deviation of bw_lim_avg valuecpu.COM:bw_lim_stdev_2_mean 7.1676 # standard deviation of bw_lim_avg valuecpu.COM:bw_lim_stdev_2_stdev 15.5043 # standard deviation of bw_lim_avg value**Ignore: cpu.COM:bw_lim_stdev_2_TOT 165901.0000 # standard deviation of bw_lim_avg valuecpu.COM:bw_lim_stdev_3_mean 5.4799 # standard deviation of bw_lim_avg valuecpu.COM:bw_lim_stdev_3_stdev 13.3864 # standard deviation of bw_lim_avg value**Ignore: cpu.COM:bw_lim_stdev_3_TOT 165901.0000 # standard deviation of bw_lim_avg valuecpu.COM:bw_limited 3782760 # number of insts not committed due to BW limitscpu.COM:bw_limited_0 841568 # number of insts not committed due to BW limitscpu.COM:bw_limited_1 842960 # number of insts not committed due to BW limitscpu.COM:bw_limited_2 1189118 # number of insts not committed due to BW limitscpu.COM:bw_limited_3 909114 # number of insts not committed due to BW limitscpu.COM:committed_per_cycle.start_dist # Number of insts commited each cyclecpu.COM:committed_per_cycle.samples 1005154 cpu.COM:committed_per_cycle.min_value 0 0 4746 47.22% 1 273820 2724.16% 2 176446 1755.41% 3 125476 1248.33% 4 93388 929.09% 5 61204 608.90% 6 49082 488.30% 7 35082 349.02% 8 185910 1849.57% cpu.COM:committed_per_cycle.max_value 8 cpu.COM:committed_per_cycle.end_distcpu.COM:count 3701726 # Number of instructions committedcpu.COM:count_0 895416 # Number of instructions committedcpu.COM:count_1 894939 # Number of instructions committedcpu.COM:count_2 1000001 # Number of instructions committedcpu.COM:count_3 911370 # Number of instructions committedcpu.COM:loads 878865 # Number of loads committedcpu.COM:loads_0 212159 # Number of loads committedcpu.COM:loads_1 212040 # Number of loads committedcpu.COM:loads_2 238693 # Number of loads committedcpu.COM:loads_3 215973 # Number of loads committedcpu.COM:membars 0 # Number of memory barriers committedcpu.COM:membars_0 0 # Number of memory barriers committedcpu.COM:membars_1 0 # Number of memory barriers committedcpu.COM:membars_2 0 # Number of memory barriers committedcpu.COM:membars_3 0 # Number of memory barriers committedcpu.COM:refs 1328846 # Number of memory references committedcpu.COM:refs_0 321250 # Number of memory references committedcpu.COM:refs_1 321089 # Number of memory references committedcpu.COM:refs_2 359521 # Number of memory references committedcpu.COM:refs_3 326986 # Number of memory references committedcpu.COM:stores 449981 # Number of stores committedcpu.COM:stores_0 109091 # Number of stores committedcpu.COM:stores_1 109049 # Number of stores committedcpu.COM:stores_2 120828 # Number of stores committedcpu.COM:stores_3 111013 # Number of stores committedcpu.COM:swp_count 8332 # Number of s/w prefetches committedcpu.COM:swp_count_0 2004 # Number of s/w prefetches committedcpu.COM:swp_count_1 2004 # Number of s/w prefetches committedcpu.COM:swp_count_2 2263 # Number of s/w prefetches committedcpu.COM:swp_count_3 2061 # Number of s/w prefetches committedcpu.DDQ:count 160616057 # cum count of instructionscpu.DDQ:count_0 37448236 # cum count of instructionscpu.DDQ:count_1 37778563 # cum count of instructionscpu.DDQ:count_2 45654426 # cum count of instructionscpu.DDQ:count_3 39734832 # cum count of instructionscpu.DDQ:rate 90 # average number of instructionscpu.DDQ:rate_0 21 # average number of instructionscpu.DDQ:rate_1 21 # average number of instructionscpu.DDQ:rate_2 26 # average number of instructionscpu.DDQ:rate_3 22 # average number of instructionscpu.DIS:chain_creation.start_dist Inst has no outstanding IDEPS 0 0.00% # Reason that chain head was created IDEP chain reached max depth 0 0.00% # Reason that chain head was created Inst is a load 0 0.00% # Reason that chain head was created Chain has multiple chained IDEPS 0 0.00% # Reason that chain head was createdcpu.DIS:chain_creation.end_distcpu.DIS:chain_head_frac 0 # fraction of insts that are chain headscpu.DIS:chain_head_frac_0 0 # fraction of insts that are chain headscpu.DIS:chain_head_frac_1 0 # fraction of insts that are chain headscpu.DIS:chain_head_frac_2 0 # fraction of insts that are chain headscpu.DIS:chain_head_frac_3 0 # fraction of insts that are chain headscpu.DIS:chain_heads 0 # number insts that are chain headscpu.DIS:chain_heads_0 0 # number insts that are chain headscpu.DIS:chain_heads_1 0 # number insts that are chain headscpu.DIS:chain_heads_2 0 # number insts that are chain headscpu.DIS:chain_heads_3 0 # number insts that are chain headscpu.DIS:chains_insuf 0 # number of times thread had insuf chainscpu.DIS:chains_insuf_0 0 # number of times thread had insuf chainscpu.DIS:chains_insuf_1 0 # number of times thread had insuf chainscpu.DIS:chains_insuf_2 0 # number of times thread had insuf chainscpu.DIS:chains_insuf_3 0 # number of times thread had insuf chainscpu.DIS:chains_insuf_rate 0 # rate that thread had insuf chainscpu.DIS:chains_insuf_rate_0 0 # rate that thread had insuf chainscpu.DIS:chains_insuf_rate_1 0 # rate that thread had insuf chainscpu.DIS:chains_insuf_rate_2 0 # rate that thread had insuf chainscpu.DIS:chains_insuf_rate_3 0 # rate that thread had insuf chainscpu.DIS:count 4535632 # cumulative count of dispatched instscpu.DIS:count_0 1047260 # cumulative count of dispatched instscpu.DIS:count_1 1053895 # cumulative count of dispatched instscpu.DIS:count_2 1316461 # cumulative count of dispatched instscpu.DIS:count_3 1118016 # cumulative count of dispatched instscpu.DIS:insufficient_chains 0 # Number of instances where dispatch stoppedcpu.DIS:mod_n_stall_avg_free no value # avg free slots per cyclecpu.DIS:mod_n_stall_avg_free_0 no value # avg free slots per cyclecpu.DIS:mod_n_stall_avg_free_1 no value # avg free slots per cyclecpu.DIS:mod_n_stall_avg_free_2 no value # avg free slots per cyclecpu.DIS:mod_n_stall_avg_free_3 no value # avg free slots per cyclecpu.DIS:mod_n_stall_frac 0 # avg stalls per cyclecpu.DIS:mod_n_stall_frac_0 0 # avg stalls per cyclecpu.DIS:mod_n_stall_frac_1 0 # avg stalls per cyclecpu.DIS:mod_n_stall_frac_2 0 # avg stalls per cyclecpu.DIS:mod_n_stall_frac_3 0 # avg stalls per cyclecpu.DIS:mod_n_stall_free 0 # free slots when dispatch stalled due to mod-ncpu.DIS:mod_n_stall_free_0 0 # free slots when dispatch stalled due to mod-ncpu.DIS:mod_n_stall_free_1 0 # free slots when dispatch stalled due to mod-ncpu.DIS:mod_n_stall_free_2 0 # free slots when dispatch stalled due to mod-ncpu.DIS:mod_n_stall_free_3 0 # free slots when dispatch stalled due to mod-ncpu.DIS:mod_n_stalls 0 # cycles where dispatch stalled due to mod-ncpu.DIS:mod_n_stalls_0 0 # cycles where dispatch stalled due to mod-ncpu.DIS:mod_n_stalls_1 0 # cycles where dispatch stalled due to mod-ncpu.DIS:mod_n_stalls_2 0 # cycles where dispatch stalled due to mod-ncpu.DIS:mod_n_stalls_3 0 # cycles where dispatch stalled due to mod-ncpu.DIS:one_rdy_insts 0 # number of 2-op insts w/ one rdy opcpu.DIS:one_rdy_insts_0 0 # number of 2-op insts w/ one rdy opcpu.DIS:one_rdy_insts_1 0 # number of 2-op insts w/ one rdy opcpu.DIS:one_rdy_insts_2 0 # number of 2-op insts w/ one rdy opcpu.DIS:one_rdy_insts_3 0 # number of 2-op insts w/ one rdy opcpu.DIS:one_rdy_ratio no value # fraction of 2-op insts w/ one ready opcpu.DIS:one_rdy_ratio_0 no value # fraction of 2-op insts w/ one ready opcpu.DIS:one_rdy_ratio_1 no value # fraction of 2-op insts w/ one ready op
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