m5stats.txt

linux下基于c++的处理器仿真平台。具有处理器流水线

---------- Begin Simulation Statistics ----------
host_inst_rate                                  32388                       # Simulator instruction rate (inst/s)
host_mem_usage                                 192928                       # Number of bytes of host memory used
host_seconds                                 24118.89                       # Real time elapsed on the host
host_tick_rate                                 298517                       # Simulator tick rate (ticks/s)
sim_freq                                   4000000000                       # Frequency of simulated ticks
sim_insts                                   781158668                       # Number of instructions simulated
sim_seconds                                  1.799973                       # Number of seconds simulated
sim_ticks                                  7199893257                       # Number of ticks simulated
system.cpu.COM:IPB                           3.124504                       # Committed instructions per branch
system.cpu.COM:IPC                           0.108496                       # Committed instructions per cycle
system.cpu.COM:branches                     250010432                       # Number of branches committed
system.cpu.COM:bw_lim_avg                <err: div-0>                       # Avg number not committed in cycles BW limited
system.cpu.COM:bw_lim_events                        0                       # number cycles where commit BW limit reached
system.cpu.COM:bw_lim_rate                     0.0000                       # Average number not committed due to BW (over all cycles)
system.cpu.COM:bw_lim_stdev_0_mean       <err: div-0>                       # standard deviation of bw_lim_avg value
system.cpu.COM:bw_lim_stdev_0_stdev      <err: div-0>                       # standard deviation of bw_lim_avg value
**Ignore: system.cpu.COM:bw_lim_stdev_0_TOT       0.0000                       # standard deviation of bw_lim_avg value
system.cpu.COM:bw_limited                           0                       # number of insts not committed due to BW limits
system.cpu.COM:committed_per_cycle.start_dist                     # Number of insts commited each cycle
system.cpu.COM:committed_per_cycle.samples    137873601                      
system.cpu.COM:committed_per_cycle.min_value            0                      
                               0       356928     25.89%           
                               1      6521455    473.00%           
                               2      6656054    482.76%           
                               3     15959840   1157.57%           
                               4     22993762   1667.74%           
                               5       754491     54.72%           
                               6     22290008   1616.70%           
                               7     14558766   1055.95%           
                               8     47782297   3465.66%           
system.cpu.COM:committed_per_cycle.max_value            8                      
system.cpu.COM:committed_per_cycle.end_dist

system.cpu.COM:count                        781158668                       # Number of instructions committed
system.cpu.COM:loads                         10485438                       # Number of loads committed
system.cpu.COM:membars                         267027                       # Number of memory barriers committed
system.cpu.COM:refs                          17903844                       # Number of memory references committed
system.cpu.COM:stores                         7418406                       # Number of stores committed
system.cpu.COM:swp_count                       211704                       # Number of s/w prefetches committed
system.cpu.DDQ:count                      21434235834                       # cum count of instructions
system.cpu.DDQ:rate                                 3                       # average number of instructions
system.cpu.DIS:chain_creation.start_dist
     Inst has no outstanding IDEPS            0      0.00%            # Reason that chain head was created
      IDEP chain reached max depth            0      0.00%            # Reason that chain head was created
                    Inst is a load            0      0.00%            # Reason that chain head was created
  Chain has multiple chained IDEPS            0      0.00%            # Reason that chain head was created
system.cpu.DIS:chain_creation.end_dist
system.cpu.DIS:chain_head_frac                      0                       # fraction of insts that are chain heads
system.cpu.DIS:chain_heads                          0                       # number insts that are chain heads
system.cpu.DIS:chains_insuf                         0                       # number of times thread had insuf chains
system.cpu.DIS:chains_insuf_rate                    0                       # rate that thread had insuf chains
system.cpu.DIS:count                        812324051                       # cumulative count of dispatched insts
system.cpu.DIS:insufficient_chains                  0                       # Number of instances where dispatch stopped
system.cpu.DIS:mod_n_stall_avg_free          no value                       # avg free slots per cycle
system.cpu.DIS:mod_n_stall_frac                     0                       # avg stalls per cycle
system.cpu.DIS:mod_n_stall_free                     0                       # free slots when dispatch stalled due to mod-n
system.cpu.DIS:mod_n_stalls                         0                       # cycles where dispatch stalled due to mod-n
system.cpu.DIS:one_rdy_insts                        0                       # number of 2-op insts w/ one rdy op
system.cpu.DIS:one_rdy_ratio                 no value                       # fraction of 2-op insts w/ one ready op
system.cpu.DIS:op_count                     837535463                       # number of operations dispatched
system.cpu.DIS:op_rate                       0.116326                       # dispatched operations per cycle
system.cpu.DIS:rate                          0.112824                       # dispatched_insts per cycle
system.cpu.DIS:second_choice_clust                  0                       # Number of instructions dispatched to second-choice cluster
system.cpu.DIS:second_choice_stall                  0                       # Number of instructions stalled when first choice not available
system.cpu.DIS:serialize_stall_cycles         7148610                       # count of cycles dispatch stalled for serializing inst
system.cpu.DIS:serializing_insts               464106                       # count of serializing insts dispatched
system.cpu.DIS:two_input_insts                      0                       # Number of two input instructions queued
system.cpu.DIS:two_input_ratio                      0                       # fraction of all insts having 2 inputs
system.cpu.FETCH:branch_count               266934688                       # Number of branches fetched
system.cpu.FETCH:branch_rate                 0.037075                       # Number of branch fetches per cycle
system.cpu.FETCH:chance_pct                         1                       # Percentage of all fetch chances
system.cpu.FETCH:chances                    145992410                       # Number of fetch opportunities
system.cpu.FETCH:choice                     145992410                       # Number of times we fetched from our first choice
system.cpu.FETCH:count                      896034769                       # Number of instructions fetched
system.cpu.FETCH:decisions                  145992410                       # number of times the fetch stage chose between threads
system.cpu.FETCH:idle_cycles               7053900848                       # number of cycles where fetch stage was idle
system.cpu.FETCH:idle_icache_blocked_cycles            0                       # number of cycles where fetch was idle due to icache blocked
system.cpu.FETCH:idle_rate                      97.97                       # percent of cycles fetch stage was idle
system.cpu.FETCH:prio_changes                       0                       # Number of times priorities were changed
system.cpu.FETCH:rate                        0.124451                       # Number of inst fetches per cycle
system.cpu.FETCH:rate_dist.start_dist                          # Number of instructions fetched each cycle (Total)
system.cpu.FETCH:rate_dist.samples          145992410                      
system.cpu.FETCH:rate_dist.min_value                0                      
                               0       196709     13.47%           
                               1       347751     23.82%           
                               2       628624     43.06%           
                               3      2968917    203.36%           
                               4       988347     67.70%           
                               5       408479     27.98%           
                               6    121581296   8327.92%           
                               7       938836     64.31%           
                               8     17933451   1228.38%           
system.cpu.FETCH:rate_dist.max_value                8                      
system.cpu.FETCH:rate_dist.end_dist

system.cpu.FETCH:rate_dist_0.start_dist                        # Number of instructions fetched each cycle (Thread 0)
system.cpu.FETCH:rate_dist_0.samples        145992410                      
system.cpu.FETCH:rate_dist_0.min_value              0                      
                               0       196709     13.47%           
                               1       347751     23.82%           
                               2       628624     43.06%           
                               3      2968917    203.36%           
                               4       988347     67.70%           
                               5       408479     27.98%           
                               6    121581296   8327.92%           
                               7       938836     64.31%           
                               8     17933451   1228.38%           
system.cpu.FETCH:rate_dist_0.max_value              8                      
system.cpu.FETCH:rate_dist_0.end_dist

system.cpu.IFQ:count                       5370236211                       # cumulative IFQ occupancy
system.cpu.IFQ:full_count                   159466415                       # cumulative IFQ full count
system.cpu.IFQ:full_rate                     2.214844                       # fraction of time (cycle's) IFQ was full
system.cpu.IFQ:latency                       6.610953                       # avg IFQ occupant latency (cycle's)
system.cpu.IFQ:occupancy                     0.745877                       # avg IFQ occupancy (inst's)
system.cpu.IFQ:qfull_iq_occ                3495781829                       # Number of insts in IQ when fetch-queue full
system.cpu.IFQ:qfull_iq_occ_dist_0.start_dist                     # Number of insts in IQ when fetch-queue full
system.cpu.IFQ:qfull_iq_occ_dist_0.samples     34963479                      
system.cpu.IFQ:qfull_iq_occ_dist_0.min_value            0                      
                               0      5081776   1453.45%           
                              10       358941    102.66%           
                              20       413497    118.27%           
                              30       700541    200.36%           
                              40       701234    200.56%           
                              50       294344     84.19%           
                              60       654573    187.22%           
                              70       190644     54.53%           
                              80        94566     27.05%           
                              90      4079377   1166.75%           
                             100       615365    176.00%           
                             110        59423     17.00%           
                             120     20688848   5917.27%           
                             130        20944      5.99%           
                             140        38226     10.93%           
                             150         7468      2.14%           
                             160        20355      5.82%           
                             170        72770     20.81%           
                             180       215631     61.67%           
                             190         7153      2.05%           
                             200         4246      1.21%           
                             210         1936      0.55%           
                             220         4574      1.31%           
                             230        14058      4.02%           
                             240         5094      1.46%           
                             250       617895    176.73%           
                             260            0      0.00%           
system.cpu.IFQ:qfull_iq_occ_dist_0.max_value          256                      
system.cpu.IFQ:qfull_iq_occ_dist_0.end_dist

system.cpu.IFQ:qfull_rob_occ               6739823539                       # Number of insts in ROB when fetch-queue full
system.cpu.IFQ:qfull_rob_occ_dist_0.start_dist                     # Number of insts in ROB when fetch-queue full
system.cpu.IFQ:qfull_rob_occ_dist_0.samples     34963479                      
system.cpu.IFQ:qfull_rob_occ_dist_0.min_value            1                      
                               0       621996    177.90%           
                              10       834255    238.61%           
                              20       628586    179.78%           
                              30       204435     58.47%           
                              40       156964     44.89%           
                              50        90077     25.76%           
                              60       161793     46.27%           
                              70       526331    150.54%           
                              80       484683    138.63%           
                              90       327602     93.70%           
                             100      4051396   1158.75%           
                             110       300622     85.98%           
                             120       291227     83.29%           
                             130       571685    163.51%           
                             140       213363     61.02%           
                             150       172919     49.46%           
                             160        91152     26.07%           
                             170        47407     13.56%           
                             180       235144     67.25%           
                             190     20624967   5899.00%           
                             200       278424     79.63%           
                             210        66538     19.03%           
                             220        54186     15.50%           
                             230        39198     11.21%           
                             240        26573      7.60%           
                             250       211420     60.47%           
                             260        21554      6.16%           
                             270        17809      5.09%           
                             280        18897      5.40%           
                             290        12677      3.63%