m5stats.txt

linux下基于c++的处理器仿真平台。具有处理器流水线

---------- Begin Simulation Statistics ----------
cpu.dcache.avg_blocked_cycles_no_mshrs   <err: div-0>                       # average number of cycles each access was blocked
cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
cpu.dcache.avg_refs                        633.527675                       # Average number of references to valid blocks.
cpu.dcache.blocked_no_mshrs                         0                       # number of cycles access was blocked
cpu.dcache.blocked_no_targets                       0                       # number of cycles access was blocked
cpu.dcache.blocked_cycles_no_mshrs                  0                       # number of cycles access was blocked
cpu.dcache.blocked_cycles_no_targets                0                       # number of cycles access was blocked
cpu.dcache.cache_copies                             0                       # number of cache copies performed
cpu.dcache.demand_accesses                     343914                       # number of demand (read+write) accesses
cpu.dcache.demand_avg_miss_latency                  0                       # average overall miss latency
cpu.dcache.demand_hits                         343190                       # number of demand (read+write) hits
cpu.dcache.demand_miss_latency                      0                       # number of demand (read+write) miss cycles
cpu.dcache.demand_miss_rate                  0.002105                       # miss rate for demand accesses
cpu.dcache.demand_misses                          724                       # number of demand (read+write) misses
cpu.dcache.fast_writes                              0                       # number of fast writes performed
cpu.dcache.overall_accesses                    343914                       # number of overall (read+write) accesses
cpu.dcache.overall_avg_miss_latency                 0                       # average overall miss latency
cpu.dcache.overall_hits                        343190                       # number of overall hits
cpu.dcache.overall_miss_latency                     0                       # number of overall miss cycles
cpu.dcache.overall_miss_rate                 0.002105                       # miss rate for overall accesses
cpu.dcache.overall_misses                         724                       # number of overall misses
cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
cpu.dcache.prefetcher.num_hwpf_evicted              0                       # number of hwpf removed due to no buffer left
cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
cpu.dcache.prefetcher.num_hwpf_issued               0                       # number of hwpf issued
cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
cpu.dcache.protocol.hwpf_invalid                    0                       # hard prefetch misses to invalid blocks
cpu.dcache.protocol.read_invalid                  372                       # read misses to invalid blocks
cpu.dcache.protocol.snoop_inv_exclusive             0                       # Invalidate snoops on exclusive blocks
cpu.dcache.protocol.snoop_inv_invalid               0                       # Invalidate snoops on invalid blocks
cpu.dcache.protocol.snoop_inv_modified              0                       # Invalidate snoops on modified blocks
cpu.dcache.protocol.snoop_inv_owned                 0                       # Invalidate snoops on owned blocks
cpu.dcache.protocol.snoop_inv_shared                0                       # Invalidate snoops on shared blocks
cpu.dcache.protocol.snoop_read_exclusive            0                       # read snoops on exclusive blocks
cpu.dcache.protocol.snoop_read_modified             0                       # read snoops on modified blocks
cpu.dcache.protocol.snoop_read_owned                0                       # read snoops on owned blocks
cpu.dcache.protocol.snoop_read_shared               0                       # read snoops on shared blocks
cpu.dcache.protocol.snoop_readex_exclusive            0                       # readEx snoops on exclusive blocks
cpu.dcache.protocol.snoop_readex_modified            0                       # readEx snoops on modified blocks
cpu.dcache.protocol.snoop_readex_owned              0                       # readEx snoops on owned blocks
cpu.dcache.protocol.snoop_readex_shared             0                       # readEx snoops on shared blocks
cpu.dcache.protocol.snoop_upgrade_owned             0                       # upgrade snoops on owned blocks
cpu.dcache.protocol.snoop_upgrade_shared            0                       # upgradee snoops on shared blocks
cpu.dcache.protocol.snoop_writeinv_exclusive            0                       # WriteInvalidate snoops on exclusive blocks
cpu.dcache.protocol.snoop_writeinv_invalid            0                       # WriteInvalidate snoops on invalid blocks
cpu.dcache.protocol.snoop_writeinv_modified            0                       # WriteInvalidate snoops on modified blocks
cpu.dcache.protocol.snoop_writeinv_owned            0                       # WriteInvalidate snoops on owned blocks
cpu.dcache.protocol.snoop_writeinv_shared            0                       # WriteInvalidate snoops on shared blocks
cpu.dcache.protocol.swpf_invalid                    0                       # soft prefetch misses to invalid blocks
cpu.dcache.protocol.write_invalid                 170                       # write misses to invalid blocks
cpu.dcache.protocol.write_owned                     0                       # write misses to owned blocks
cpu.dcache.protocol.write_shared                  182                       # write misses to shared blocks
cpu.dcache.read_accesses                       249653                       # number of read accesses(hits+misses)
cpu.dcache.read_hits                           249281                       # number of read hits
cpu.dcache.read_miss_rate                    0.001490                       # miss rate for read accesses
cpu.dcache.read_misses                            372                       # number of read misses
cpu.dcache.replacements                            80                       # number of replacements
cpu.dcache.sampled_refs                           542                       # Sample count of references to valid blocks.
cpu.dcache.tagsinuse                       357.976118                       # Cycle average of tags in use
cpu.dcache.total_refs                          343372                       # Total number of references to valid blocks.
cpu.dcache.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
cpu.dcache.write_accesses                       94261                       # number of write accesses(hits+misses)
cpu.dcache.write_hits                           93909                       # number of write hits
cpu.dcache.write_miss_rate                   0.003734                       # miss rate for write accesses
cpu.dcache.write_misses                           352                       # number of write misses
cpu.dcache.writebacks                               0                       # number of writebacks
cpu.icache.avg_blocked_cycles_no_mshrs   <err: div-0>                       # average number of cycles each access was blocked
cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
cpu.icache.avg_refs                       1847.049281                       # Average number of references to valid blocks.
cpu.icache.blocked_no_mshrs                         0                       # number of cycles access was blocked
cpu.icache.blocked_no_targets                       0                       # number of cycles access was blocked
cpu.icache.blocked_cycles_no_mshrs                  0                       # number of cycles access was blocked
cpu.icache.blocked_cycles_no_targets                0                       # number of cycles access was blocked
cpu.icache.cache_copies                             0                       # number of cache copies performed
cpu.icache.demand_accesses                     900000                       # number of demand (read+write) accesses
cpu.icache.demand_avg_miss_latency                  0                       # average overall miss latency
cpu.icache.demand_hits                         899513                       # number of demand (read+write) hits
cpu.icache.demand_miss_latency                      0                       # number of demand (read+write) miss cycles
cpu.icache.demand_miss_rate                  0.000541                       # miss rate for demand accesses
cpu.icache.demand_misses                          487                       # number of demand (read+write) misses
cpu.icache.fast_writes                              0                       # number of fast writes performed
cpu.icache.overall_accesses                    900000                       # number of overall (read+write) accesses
cpu.icache.overall_avg_miss_latency                 0                       # average overall miss latency