📄 m5stats.txt
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cpu.IFQ:qfull_rob_occ_dist_3.samples 277040 cpu.IFQ:qfull_rob_occ_dist_3.min_value 0 0 90405 3263.25% 10 46061 1662.61% 20 80997 2923.66% 30 34911 1260.14% 40 11833 427.12% 50 5738 207.12% 60 3367 121.53% 70 1409 50.86% 80 814 29.38% 90 217 7.83% 100 312 11.26% 110 80 2.89% 120 153 5.52% 130 116 4.19% 140 73 2.63% 150 57 2.06% 160 81 2.92% 170 27 0.97% 180 282 10.18% 190 107 3.86% 200 0 0.00% cpu.IFQ:qfull_rob_occ_dist_3.max_value 196 cpu.IFQ:qfull_rob_occ_dist_3.end_distcpu.IQ:cap_events 0 # number of cycles where IQ cap was activecpu.IQ:cap_events_0 0 # number of cycles where IQ cap was activecpu.IQ:cap_events_1 0 # number of cycles where IQ cap was activecpu.IQ:cap_events_2 0 # number of cycles where IQ cap was activecpu.IQ:cap_events_3 0 # number of cycles where IQ cap was activecpu.IQ:cap_inst 0 # number of instructions held up by IQ capcpu.IQ:cap_inst_0 0 # number of instructions held up by IQ capcpu.IQ:cap_inst_1 0 # number of instructions held up by IQ capcpu.IQ:cap_inst_2 0 # number of instructions held up by IQ capcpu.IQ:cap_inst_3 0 # number of instructions held up by IQ capcpu.IQ:residence:(null).start_dist # cycles from dispatch to issuecpu.IQ:residence:(null).samples 0 cpu.IQ:residence:(null).min_value 0 0 0 2 0 4 0 6 0 8 0 10 0 12 0 14 0 16 0 18 0 20 0 22 0 24 0 26 0 28 0 30 0 32 0 34 0 36 0 38 0 40 0 42 0 44 0 46 0 48 0 50 0 52 0 54 0 56 0 58 0 60 0 62 0 64 0 66 0 68 0 70 0 72 0 74 0 76 0 78 0 80 0 82 0 84 0 86 0 88 0 90 0 92 0 94 0 96 0 98 0 cpu.IQ:residence:(null).max_value 0 cpu.IQ:residence:(null).end_distcpu.IQ:residence:IntAlu.start_dist # cycles from dispatch to issuecpu.IQ:residence:IntAlu.samples 1861890 cpu.IQ:residence:IntAlu.min_value 1 0 165034 886.38% 886.38% 2 226418 1216.07% 2102.44% 4 208004 1117.17% 3219.61% 6 267841 1438.54% 4658.15% 8 252040 1353.68% 6011.83% 10 226517 1216.60% 7228.43% 12 160439 861.70% 8090.13% 14 122656 658.77% 8748.90% 16 84199 452.22% 9201.12% 18 54040 290.24% 9491.37% 20 30495 163.79% 9655.15% 22 15842 85.09% 9740.24% 24 7607 40.86% 9781.09% 26 3580 19.23% 9800.32% 28 2093 11.24% 9811.56% 30 1400 7.52% 9819.08% 32 941 5.05% 9824.14% 34 731 3.93% 9828.06% 36 617 3.31% 9831.38% 38 486 2.61% 9833.99% 40 456 2.45% 9836.44% 42 889 4.77% 9841.21% 44 576 3.09% 9844.30% 46 369 1.98% 9846.29% 48 269 1.44% 9847.73% 50 221 1.19% 9848.92% 52 230 1.24% 9850.15% 54 308 1.65% 9851.81% 56 238 1.28% 9853.08% 58 231 1.24% 9854.33% 60 267 1.43% 9855.76% 62 204 1.10% 9856.86% 64 263 1.41% 9858.27% 66 231 1.24% 9859.51% 68 249 1.34% 9860.85% 70 231 1.24% 9862.09% 72 186 1.00% 9863.09% 74 203 1.09% 9864.18% 76 198 1.06% 9865.24% 78 205 1.10% 9866.34% 80 209 1.12% 9867.46% 82 222 1.19% 9868.65% 84 223 1.20% 9869.85% 86 206 1.11% 9870.96% 88 253 1.36% 9872.32% 90 200 1.07% 9873.39% 92 254 1.36% 9874.76% 94 249 1.34% 9876.09% 96 286 1.54% 9877.63% 98 321 1.72% 9879.35%cpu.IQ:residence:IntAlu.overflows 22463 cpu.IQ:residence:IntAlu.max_value 1150 cpu.IQ:residence:IntAlu.end_distcpu.IQ:residence:IntMult.start_dist # cycles from dispatch to issuecpu.IQ:residence:IntMult.samples 705 cpu.IQ:residence:IntMult.min_value 1 0 58 822.70% 822.70% 2 98 1390.07% 2212.77% 4 73 1035.46% 3248.23% 6 165 2340.43% 5588.65% 8 106 1503.55% 7092.20% 10 75 1063.83% 8156.03% 12 58 822.70% 8978.72% 14 36 510.64% 9489.36%
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