📄 m5stats.txt
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180 20493 39.00% 181 20518 39.04% 182 20611 39.22% 183 20336 38.70% 184 20506 39.02% 185 20562 39.13% 186 20666 39.33% 187 20618 39.24% 188 20524 39.06% 189 20519 39.05% 190 20537 39.08% 191 20673 39.34% 192 20485 38.98% 193 20585 39.17% 194 20570 39.14% 195 20507 39.02% 196 20539 39.08% 197 20530 39.07% 198 20496 39.00% 199 20571 39.15% 200 20544 39.09% 201 20367 38.76% 202 20526 39.06% 203 20415 38.85% 204 20546 39.10% 205 20326 38.68% 206 20348 38.72% 207 20438 38.89% 208 20587 39.18% 209 20628 39.25% 210 20666 39.33% 211 20618 39.24% 212 20425 38.87% 213 20338 38.70% 214 20669 39.33% 215 20417 38.85% 216 20575 39.15% 217 20373 38.77% 218 20644 39.28% 219 20657 39.31% 220 20574 39.15% 221 20305 38.64% 222 20556 39.12% 223 20403 38.83% 224 20640 39.28% 225 20681 39.35% 226 20677 39.35% 227 20495 39.00% 228 20514 39.04% 229 20529 39.07% 230 20502 39.01% 231 20519 39.05% 232 20563 39.13% 233 20664 39.32% 234 20548 39.10% 235 20740 39.47% 236 20524 39.06% 237 20476 38.96% 238 20692 39.38% 239 20676 39.35% 240 20537 39.08% 241 20512 39.03% 242 20547 39.10% 243 20331 38.69% 244 20379 38.78% 245 20455 38.92% 246 20473 38.96% 247 20320 38.67% 248 20409 38.84% 249 20402 38.82% 250 20465 38.94% 251 20839 39.66% 252 20475 38.96% 253 20680 39.35% 254 20603 39.21% 255 20412 38.84% 256 0 0.00% L2.set_access_dist.max_value 255 L2.set_access_dist.end_distL2.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutionsL2.tagsinuse 2045.109535 # Cycle average of tags in useL2.total_refs 5250016 # Total number of references to valid blocks.L2.warmup_cycle 32220 # Cycle when the warmup percentage was hit.L2.write_avg_mshr_uncacheable_latency 1023.705683 # average write mshr uncacheable latencyL2.write_mshr_uncacheable 264348 # number of write MSHR uncacheableL2.write_mshr_uncacheable_latency 270614550 # number of write MSHR uncacheable cyclesL2.writeback_accesses 1796123 # number of writeback accesses(hits+misses)L2.writeback_hits 1795421 # number of writeback hitsL2.writeback_miss_rate 0.000391 # miss rate for writeback accessesL2.writeback_misses 702 # number of writeback missesL2.writeback_mshr_miss_rate 0.000391 # mshr miss rate for writeback accessesL2.writeback_mshr_misses 702 # number of writeback MSHR missesL2.writebacks 2222 # number of writebacksSDRAM.accesses 764056 # total number of accessesSDRAM.bytes_requested 765983 # total number of bytes requestedSDRAM.bytes_sent 513437 # total number of bytes sentSDRAM.compressed_responses 6495 # total number of accesses that are compressedcheckMem.page_count 0 # total number of pages allocatedcheckMem.page_mem 0 # total size of memory pages allocatedcheckMem.ptab_accesses 7750075 # total page table accessesscheckMem.ptab_miss_rate 0.0000 # first level page table miss ratecheckMem.ptab_misses 0 # total first level page table misseshost_mem_usage 12600 # Number of bytes of host memory usedhost_seconds 68.23 # Real time elapsed on the hosthost_tick_rate 543712 # Simulator tick rate (ticks/s)mainMem.page_count 0 # total number of pages allocatedmainMem.page_mem 0 # total size of memory pages allocatedmainMem.ptab_accesses 770000 # total page table accessessmainMem.ptab_miss_rate 0.0000 # first level page table miss ratemainMem.ptab_misses 0 # total first level page table missessim_freq 200000000 # Frequency of simulated tickssim_seconds 0.185476 # Number of seconds simulatedsim_ticks 37095133 # Number of ticks simulatedtest.num_copies 0 # number of copy accesses completedtest.num_reads 5000000 # number of read accesses completedtest.num_writes 2690489 # number of write accesses completedtoL2Bus.addr_idle_cycles 7679236 # number of cycles bus was idletoL2Bus.addr_idle_fraction 0.207015 # fraction of time addr bus was idletoL2Bus.addr_queued 14.925941 # average queueing delay seen by bus requesttoL2Bus.addr_queued_cycles 93678072 # total number of queued cycles for all requeststoL2Bus.addr_requests 6276192 # number of transmissions on bustoL2Bus.bus_blocked 159466 # number of times bus was blockedtoL2Bus.bus_blocked_cycles 19804408 # number of cycles bus was blockedtoL2Bus.bus_blocked_fraction 0.533882 # fraction of time bus was blockedtoL2Bus.data_idle_cycles 25071448 # number of cycles bus was idletoL2Bus.data_idle_fraction 0.675869 # fraction of time data bus was idletoL2Bus.data_queued 4.902757 # average queueing delay seen by bus requesttoL2Bus.data_queued_cycles 19372566 # total number of queued cycles for all requeststoL2Bus.data_requests 3951362 # number of transmissions on bustoL2Bus.null_grants 0 # number of null grants (wasted cycles)toMemBus.addr_idle_cycles 32981512 # number of cycles bus was idletoMemBus.addr_idle_fraction 0.889106 # fraction of time addr bus was idletoMemBus.addr_queued 12.308439 # average queueing delay seen by bus requesttoMemBus.addr_queued_cycles 12657962 # total number of queued cycles for all requeststoMemBus.addr_requests 1028397 # number of transmissions on bustoMemBus.bus_blocked 0 # number of times bus was blockedtoMemBus.bus_blocked_cycles 0 # number of cycles bus was blockedtoMemBus.bus_blocked_fraction 0 # fraction of time bus was blockedtoMemBus.data_idle_cycles 34030496 # number of cycles bus was idletoMemBus.data_idle_fraction 0.917384 # fraction of time data bus was idletoMemBus.data_queued 11.119363 # average queueing delay seen by bus requesttoMemBus.data_queued_cycles 5523788 # total number of queued cycles for all requeststoMemBus.data_requests 496772 # number of transmissions on bustoMemBus.null_grants 0 # number of null grants (wasted cycles)---------- End Simulation Statistics ----------⌨️ 快捷键说明
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