📄 m5stats.txt
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180 20400 38.83% 181 20467 38.96% 182 20566 39.15% 183 20300 38.64% 184 20410 38.85% 185 20323 38.69% 186 20349 38.74% 187 20436 38.90% 188 20613 39.24% 189 20434 38.90% 190 20723 39.45% 191 20529 39.08% 192 20512 39.05% 193 20402 38.84% 194 20555 39.13% 195 20494 39.01% 196 20310 38.66% 197 20524 39.07% 198 20311 38.66% 199 20448 38.92% 200 20415 38.86% 201 20494 39.01% 202 20301 38.64% 203 20531 39.08% 204 20417 38.87% 205 20648 39.31% 206 20440 38.91% 207 20570 39.16% 208 20553 39.12% 209 20535 39.09% 210 20482 38.99% 211 20587 39.19% 212 20358 38.75% 213 20545 39.11% 214 20426 38.88% 215 20578 39.17% 216 20555 39.13% 217 20376 38.79% 218 20464 38.95% 219 20423 38.88% 220 20421 38.87% 221 20528 39.08% 222 20312 38.67% 223 20442 38.91% 224 20681 39.37% 225 20640 39.29% 226 20541 39.10% 227 20724 39.45% 228 20385 38.80% 229 20467 38.96% 230 20478 38.98% 231 20434 38.90% 232 20589 39.19% 233 20412 38.86% 234 20719 39.44% 235 20534 39.09% 236 20377 38.79% 237 20722 39.45% 238 20518 39.06% 239 20552 39.12% 240 20536 39.09% 241 20418 38.87% 242 20423 38.88% 243 20363 38.76% 244 20450 38.93% 245 20546 39.11% 246 20564 39.15% 247 20356 38.75% 248 20450 38.93% 249 20442 38.91% 250 20463 38.95% 251 20520 39.06% 252 20739 39.48% 253 20366 38.77% 254 20611 39.23% 255 20628 39.27% 256 0 0.00% L2.set_access_dist.max_value 255 L2.set_access_dist.end_distL2.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutionsL2.tagsinuse 2045.222867 # Cycle average of tags in useL2.total_refs 5248249 # Total number of references to valid blocks.L2.warmup_cycle 29456 # Cycle when the warmup percentage was hit.L2.write_avg_mshr_uncacheable_latency 1023.700302 # average write mshr uncacheable latencyL2.write_mshr_uncacheable 265200 # number of write MSHR uncacheableL2.write_mshr_uncacheable_latency 271485320 # number of write MSHR uncacheable cyclesL2.writeback_accesses 1793944 # number of writeback accesses(hits+misses)L2.writeback_hits 1793246 # number of writeback hitsL2.writeback_miss_rate 0.000389 # miss rate for writeback accessesL2.writeback_misses 698 # number of writeback missesL2.writeback_mshr_miss_rate 0.000389 # mshr miss rate for writeback accessesL2.writeback_mshr_misses 698 # number of writeback MSHR missesL2.writebacks 2275 # number of writebacksSDRAM.accesses 764780 # total number of accessesSDRAM.bytes_requested 768956 # total number of bytes requestedSDRAM.bytes_sent 513540 # total number of bytes sentSDRAM.compressed_responses 6598 # total number of accesses that are compressedcheckMem.page_count 0 # total number of pages allocatedcheckMem.page_mem 0 # total size of memory pages allocatedcheckMem.ptab_accesses 7750947 # total page table accessesscheckMem.ptab_miss_rate 0.0000 # first level page table miss ratecheckMem.ptab_misses 0 # total first level page table misseshost_mem_usage 5328 # Number of bytes of host memory usedhost_seconds 315.44 # Real time elapsed on the hosthost_tick_rate 117878 # Simulator tick rate (ticks/s)mainMem.page_count 0 # total number of pages allocatedmainMem.page_mem 0 # total size of memory pages allocatedmainMem.ptab_accesses 770627 # total page table accessessmainMem.ptab_miss_rate 0.0000 # first level page table miss ratemainMem.ptab_misses 0 # total first level page table missessim_freq 200000000 # Frequency of simulated tickssim_seconds 0.185918 # Number of seconds simulatedsim_ticks 37183647 # Number of ticks simulatedtest.num_copies 0 # number of copy accesses completedtest.num_reads 5000000 # number of read accesses completedtest.num_writes 2691236 # number of write accesses completedtoL2Bus.addr_idle_cycles 7701162 # number of cycles bus was idletoL2Bus.addr_idle_fraction 0.207112 # fraction of time addr bus was idletoL2Bus.addr_queued 14.958391 # average queueing delay seen by bus requesttoL2Bus.addr_queued_cycles 93878086 # total number of queued cycles for all requeststoL2Bus.addr_requests 6275948 # number of transmissions on bustoL2Bus.bus_blocked 160624 # number of times bus was blockedtoL2Bus.bus_blocked_cycles 19893854 # number of cycles bus was blockedtoL2Bus.bus_blocked_fraction 0.535016 # fraction of time bus was blockedtoL2Bus.data_idle_cycles 25162160 # number of cycles bus was idletoL2Bus.data_idle_fraction 0.676700 # fraction of time data bus was idletoL2Bus.data_queued 4.899308 # average queueing delay seen by bus requesttoL2Bus.data_queued_cycles 19360095 # total number of queued cycles for all requeststoL2Bus.data_requests 3951598 # number of transmissions on bustoL2Bus.null_grants 0 # number of null grants (wasted cycles)toMemBus.addr_idle_cycles 33063752 # number of cycles bus was idletoMemBus.addr_idle_fraction 0.889201 # fraction of time addr bus was idletoMemBus.addr_queued 12.303839 # average queueing delay seen by bus requesttoMemBus.addr_queued_cycles 12672634 # total number of queued cycles for all requeststoMemBus.addr_requests 1029974 # number of transmissions on bustoMemBus.bus_blocked 0 # number of times bus was blockedtoMemBus.bus_blocked_cycles 0 # number of cycles bus was blockedtoMemBus.bus_blocked_fraction 0 # fraction of time bus was blockedtoMemBus.data_idle_cycles 34116176 # number of cycles bus was idletoMemBus.data_idle_fraction 0.917505 # fraction of time data bus was idletoMemBus.data_queued 11.062030 # average queueing delay seen by bus requesttoMemBus.data_queued_cycles 5493404 # total number of queued cycles for all requeststoMemBus.data_requests 496600 # number of transmissions on bustoMemBus.null_grants 0 # number of null grants (wasted cycles)---------- End Simulation Statistics ----------⌨️ 快捷键说明
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