m5stats.txt

linux下基于c++的处理器仿真平台。具有处理器流水线

---------- Begin Simulation Statistics ----------
L1.avg_blocked_cycles_no_mshrs               3.809116                       # average number of cycles each access was blocked
L1.avg_blocked_cycles_no_targets         <err: div-0>                       # average number of cycles each access was blocked
L1.avg_refs                                  1.004372                       # Average number of references to valid blocks.
L1.blocked_no_mshrs                            200216                       # number of cycles access was blocked
L1.blocked_no_targets                               0                       # number of cycles access was blocked
L1.blocked_cycles_no_mshrs                     762646                       # number of cycles access was blocked
L1.blocked_cycles_no_targets                        0                       # number of cycles access was blocked
L1.cache_copies                                     0                       # number of cache copies performed
L1.demand_accesses                            6933777                       # number of demand (read+write) accesses
L1.demand_avg_miss_latency                  31.782850                       # average overall miss latency
L1.demand_avg_mshr_miss_latency             28.782856                       # average overall mshr miss latency
L1.demand_hits                                3474447                       # number of demand (read+write) hits
L1.demand_miss_latency                      109947366                       # number of demand (read+write) miss cycles
L1.demand_miss_rate                          0.498910                       # miss rate for demand accesses
L1.demand_misses                              3459330                       # number of demand (read+write) misses
L1.demand_mshr_hits                                 0                       # number of demand (read+write) MSHR hits
L1.demand_mshr_miss_latency                  99569397                       # number of demand (read+write) MSHR miss cycles
L1.demand_mshr_miss_rate                     0.498910                       # mshr miss rate for demand accesses
L1.demand_mshr_misses                         3459330                       # number of demand (read+write) MSHR misses
L1.fast_writes                                      0                       # number of fast writes performed
L1.mshr_cap_events                                  0                       # number of times MSHR cap was activated
L1.no_allocate_misses                               0                       # Number of misses that were no-allocate
L1.overall_accesses                           6933777                       # number of overall (read+write) accesses
L1.overall_avg_miss_latency                 31.782850                       # average overall miss latency
L1.overall_avg_mshr_miss_latency            28.782856                       # average overall mshr miss latency
L1.overall_avg_mshr_uncacheable_latency   1047.985717                       # average overall mshr uncacheable latency
L1.overall_hits                               3474447                       # number of overall hits
L1.overall_miss_latency                     109947366                       # number of overall miss cycles
L1.overall_miss_rate                         0.498910                       # miss rate for overall accesses
L1.overall_misses                             3459330                       # number of overall misses
L1.overall_mshr_hits                                0                       # number of overall MSHR hits
L1.overall_mshr_miss_latency                 99569397                       # number of overall MSHR miss cycles
L1.overall_mshr_miss_rate                    0.498910                       # mshr miss rate for overall accesses
L1.overall_mshr_misses                        3459330                       # number of overall MSHR misses
L1.overall_mshr_uncacheable_latency         793833461                       # number of overall MSHR uncacheable cycles
L1.overall_mshr_uncacheable_misses             757485                       # number of overall MSHR uncacheable misses
L1.prefetcher.num_hwpf_already_in_cache             0                       # number of hwpf that were already in the cache
L1.prefetcher.num_hwpf_already_in_mshr              0                       # number of hwpf that were already in mshr
L1.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
L1.prefetcher.num_hwpf_evicted                      0                       # number of hwpf removed due to no buffer left
L1.prefetcher.num_hwpf_identified                   0                       # number of hwpf identified
L1.prefetcher.num_hwpf_issued                       0                       # number of hwpf issued
L1.prefetcher.num_hwpf_removed_MSHR_hit             0                       # number of hwpf removed because MSHR allocated
L1.prefetcher.num_hwpf_span_page                    0                       # number of hwpf spanning a virtual page
L1.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
L1.read_accesses                              4507731                       # number of read accesses(hits+misses)
L1.read_avg_miss_latency                    31.778405                       # average read miss latency
L1.read_avg_mshr_miss_latency               28.778410                       # average read mshr miss latency
L1.read_avg_mshr_uncacheable_latency      1046.786026                       # average read mshr uncacheable latency
L1.read_hits                                  2258518                       # number of read hits
L1.read_miss_latency                         71476402                       # number of read miss cycles
L1.read_miss_rate                            0.498968                       # miss rate for read accesses
L1.read_misses                                2249213                       # number of read misses
L1.read_mshr_miss_latency                    64728775                       # number of read MSHR miss cycles
L1.read_mshr_miss_rate                       0.498968                       # mshr miss rate for read accesses
L1.read_mshr_misses                           2249213                       # number of read MSHR misses
L1.read_mshr_uncacheable                       492285                       # number of read MSHR uncacheable
L1.read_mshr_uncacheable_latency            515317059                       # number of read MSHR uncacheable cycles
L1.replacements                               3458299                       # number of replacements
L1.sampled_refs                               3459323                       # Sample count of references to valid blocks.
L1.soft_prefetch_mshr_full                          0                       # number of mshr full events for SW prefetching instrutions
L1.tagsinuse                              1023.516270                       # Cycle average of tags in use
L1.total_refs                                 3474447                       # Total number of references to valid blocks.
L1.warmup_cycle                                 61978                       # Cycle when the warmup percentage was hit.
L1.write_accesses                             2426046                       # number of write accesses(hits+misses)
L1.write_avg_miss_latency                   31.791111                       # average write miss latency
L1.write_avg_mshr_miss_latency              28.791119                       # average write mshr miss latency
L1.write_avg_mshr_uncacheable_latency     1050.212677                       # average write mshr uncacheable latency
L1.write_hits                                 1215929                       # number of write hits
L1.write_miss_latency                        38470964                       # number of write miss cycles
L1.write_miss_rate                           0.498802                       # miss rate for write accesses
L1.write_misses                               1210117                       # number of write misses
L1.write_mshr_miss_latency                   34840622                       # number of write MSHR miss cycles
L1.write_mshr_miss_rate                      0.498802                       # mshr miss rate for write accesses
L1.write_mshr_misses                          1210117                       # number of write MSHR misses
L1.write_mshr_uncacheable                      265200                       # number of write MSHR uncacheable
L1.write_mshr_uncacheable_latency           278516402                       # number of write MSHR uncacheable cycles
L1.writebacks                                 1793944                       # number of writebacks
L2.advance_pool_dist.start_dist                                # Dist. of Repl. across pools
L2.advance_pool_dist.samples                   353740                      
L2.advance_pool_dist.min_value                      0                      
                               0         5208    147.23%           
                               1          740     20.92%           
                               2          269      7.60%           
                               3          135      3.82%           
                               4           70      1.98%           
                               5           64      1.81%           
                               6           53      1.50%           
                               7           70      1.98%           
                               8           99      2.80%           
                               9           80      2.26%           
                              10         2015     56.96%           
                              11         2015     56.96%           
                              12         2015     56.96%           
                              13         2015     56.96%           
                              14         2015     56.96%           
                              15       334567   9457.99%           
                              16         2310     65.30%           
L2.advance_pool_dist.max_value                     16                      
L2.advance_pool_dist.end_dist

L2.avg_blocked_cycles_no_mshrs             163.704981                       # average number of cycles each access was blocked
L2.avg_blocked_cycles_no_targets         <err: div-0>                       # average number of cycles each access was blocked
L2.avg_refs                               1214.029378                       # Average number of references to valid blocks.
L2.blocked_no_mshrs                               522                       # number of cycles access was blocked
L2.blocked_no_targets                               0                       # number of cycles access was blocked
L2.blocked_cycles_no_mshrs                      85454                       # number of cycles access was blocked
L2.blocked_cycles_no_targets                        0                       # number of cycles access was blocked
L2.cache_copies                                     0                       # number of cache copies performed
L2.demand_accesses                            3459326                       # number of demand (read+write) accesses
L2.demand_avg_miss_latency                 932.199861                       # average overall miss latency
L2.demand_avg_mshr_miss_latency            914.271571                       # average overall mshr miss latency
L2.demand_hits                                3455003                       # number of demand (read+write) hits
L2.demand_miss_latency                        4029900                       # number of demand (read+write) miss cycles
L2.demand_miss_rate                          0.001250                       # miss rate for demand accesses
L2.demand_misses                                 4323                       # number of demand (read+write) misses
L2.demand_mshr_hits                                 0                       # number of demand (read+write) MSHR hits
L2.demand_mshr_miss_latency                   3952396                       # number of demand (read+write) MSHR miss cycles
L2.demand_mshr_miss_rate                     0.001250                       # mshr miss rate for demand accesses
L2.demand_mshr_misses                            4323                       # number of demand (read+write) MSHR misses
L2.demote_pool_dist.start_dist                                 # Dist. of Repl. across pools
L2.demote_pool_dist.samples                    152448                      
L2.demote_pool_dist.min_value                       0                      
                               0       132445   8687.88%           
                               1         5913    387.87%           
                               2         2161    141.75%           
                               3         1967    129.03%           
                               4         1965    128.90%           
                               5         1983    130.08%           
                               6         1996    130.93%           
                               7         1995    130.86%           
                               8           35      2.30%           
                               9            5      0.33%           
                              10            1      0.07%           
                              11            0      0.00%           
                              12            0      0.00%           
                              13            0      0.00%           
                              14            0      0.00%           
                              15            0      0.00%           
                              16         1982    130.01%           
L2.demote_pool_dist.max_value                      16                      
L2.demote_pool_dist.end_dist

L2.fast_writes                                      0                       # number of fast writes performed
L2.hash_hit                                   5248249                       # Total of hites in hash table
L2.hash_miss                                     5021                       # Total of misses in hash table
L2.hit_depth_total                            5248249                       # Total of hit depths
L2.hit_hash_depth_dist.start_dist                              # Dist. of Hash lookup depths