📄 m5stats.txt
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86 0 88 0 90 0 92 0 94 0 96 0 98 0 system.cpu0.IQ:residence:IntDiv.max_value 0 system.cpu0.IQ:residence:IntDiv.end_distsystem.cpu0.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issuesystem.cpu0.IQ:residence:FloatAdd.samples 6447 system.cpu0.IQ:residence:FloatAdd.min_value 1 0 1051 1630.22% 1630.22% 2 809 1254.85% 2885.06% 4 1139 1766.71% 4651.78% 6 1457 2259.97% 6911.74% 8 1 1.55% 6913.29% 10 2 3.10% 6916.40% 12 1 1.55% 6917.95% 14 1 1.55% 6919.50% 16 29 44.98% 6964.48% 18 31 48.08% 7012.56% 20 4 6.20% 7018.77% 22 2 3.10% 7021.87% 24 1860 2885.06% 9906.93% 26 12 18.61% 9925.55% 28 0 0.00% 9925.55% 30 0 0.00% 9925.55% 32 0 0.00% 9925.55% 34 1 1.55% 9927.10% 36 0 0.00% 9927.10% 38 0 0.00% 9927.10% 40 0 0.00% 9927.10% 42 0 0.00% 9927.10% 44 0 0.00% 9927.10% 46 0 0.00% 9927.10% 48 0 0.00% 9927.10% 50 0 0.00% 9927.10% 52 0 0.00% 9927.10% 54 1 1.55% 9928.65% 56 0 0.00% 9928.65% 58 0 0.00% 9928.65% 60 0 0.00% 9928.65% 62 1 1.55% 9930.20% 64 2 3.10% 9933.30% 66 34 52.74% 9986.04% 68 0 0.00% 9986.04% 70 0 0.00% 9986.04% 72 0 0.00% 9986.04% 74 0 0.00% 9986.04% 76 0 0.00% 9986.04% 78 0 0.00% 9986.04% 80 0 0.00% 9986.04% 82 0 0.00% 9986.04% 84 0 0.00% 9986.04% 86 0 0.00% 9986.04% 88 0 0.00% 9986.04% 90 0 0.00% 9986.04% 92 0 0.00% 9986.04% 94 2 3.10% 9989.14% 96 0 0.00% 9989.14% 98 0 0.00% 9989.14%system.cpu0.IQ:residence:FloatAdd.overflows 7 system.cpu0.IQ:residence:FloatAdd.max_value 478 system.cpu0.IQ:residence:FloatAdd.end_distsystem.cpu0.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issuesystem.cpu0.IQ:residence:FloatCmp.samples 0 system.cpu0.IQ:residence:FloatCmp.min_value 0 0 0 2 0 4 0 6 0 8 0 10 0 12 0 14 0 16 0 18 0 20 0 22 0 24 0 26 0 28 0 30 0 32 0 34 0 36 0 38 0 40 0 42 0 44 0 46 0 48 0 50 0 52 0 54 0 56 0 58 0 60 0 62 0 64 0 66 0 68 0 70 0 72 0 74 0 76 0 78 0 80 0 82 0 84 0 86 0 88 0 90 0 92 0 94 0 96 0 98 0 system.cpu0.IQ:residence:FloatCmp.max_value 0 system.cpu0.IQ:residence:FloatCmp.end_distsystem.cpu0.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issuesystem.cpu0.IQ:residence:FloatCvt.samples 0 system.cpu0.IQ:residence:FloatCvt.min_value 0 0 0 2 0 4 0 6 0 8 0 10 0 12 0 14 0 16 0 18 0 20 0 22 0 24 0 26 0 28 0 30 0 32 0 34 0 36 0 38 0 40 0 42 0 44 0 46 0 48 0 50 0 52 0 54 0 56 0 58 0 60 0 62 0 64 0 66 0 68 0 70 0 72 0 74 0 76 0 78 0 80 0 82 0 84 0 86 0 88 0 90 0 92 0 94 0 96 0 98 0 system.cpu0.IQ:residence:FloatCvt.max_value 0 system.cpu0.IQ:residence:FloatCvt.end_distsystem.cpu0.IQ:residence:FloatMult.start_dist # cycles from dispatch to issuesystem.cpu0.IQ:residence:FloatMult.samples 0 system.cpu0.IQ:residence:FloatMult.min_value 0 0 0 2 0 4 0
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