m5stats.txt

linux下基于c++的处理器仿真平台。具有处理器流水线

---------- Begin Simulation Statistics ----------
host_inst_rate                                  21857                       # Simulator instruction rate (inst/s)
host_mem_usage                                 200828                       # Number of bytes of host memory used
host_seconds                                 42182.65                       # Real time elapsed on the host
host_tick_rate                                 174301                       # Simulator tick rate (ticks/s)
sim_freq                                   4000000000                       # Frequency of simulated ticks
sim_insts                                   921968140                       # Number of instructions simulated
sim_seconds                                  1.838117                       # Number of seconds simulated
sim_ticks                                  7352469841                       # Number of ticks simulated
system.cpu0.COM:IPB                          3.098876                       # Committed instructions per branch
system.cpu0.COM:IPC                          0.104435                       # Committed instructions per cycle
system.cpu0.COM:branches                    247785752                       # Number of branches committed
system.cpu0.COM:bw_lim_avg               <err: div-0>                       # Avg number not committed in cycles BW limited
system.cpu0.COM:bw_lim_events                       0                       # number cycles where commit BW limit reached
system.cpu0.COM:bw_lim_rate                    0.0000                       # Average number not committed due to BW (over all cycles)
system.cpu0.COM:bw_lim_stdev_0_mean      <err: div-0>                       # standard deviation of bw_lim_avg value
system.cpu0.COM:bw_lim_stdev_0_stdev     <err: div-0>                       # standard deviation of bw_lim_avg value
**Ignore: system.cpu0.COM:bw_lim_stdev_0_TOT       0.0000                       # standard deviation of bw_lim_avg value
system.cpu0.COM:bw_limited                          0                       # number of insts not committed due to BW limits
system.cpu0.COM:committed_per_cycle.start_dist                     # Number of insts commited each cycle
system.cpu0.COM:committed_per_cycle.samples    134211800                      
system.cpu0.COM:committed_per_cycle.min_value            0                      
                               0       271423     20.22%           
                               1      5328814    397.05%           
                               2      2182786    162.64%           
                               3     11966576    891.62%           
                               4     30307720   2258.20%           
                               5       578824     43.13%           
                               6     29682627   2211.63%           
                               7     10893697    811.68%           
                               8     42999333   3203.84%           
system.cpu0.COM:committed_per_cycle.max_value            8                      
system.cpu0.COM:committed_per_cycle.end_dist

system.cpu0.COM:count                       767857289                       # Number of instructions committed
system.cpu0.COM:loads                         8265223                       # Number of loads committed
system.cpu0.COM:membars                        201523                       # Number of memory barriers committed
system.cpu0.COM:refs                         13949106                       # Number of memory references committed
system.cpu0.COM:stores                        5683883                       # Number of stores committed
system.cpu0.COM:swp_count                      208130                       # Number of s/w prefetches committed
system.cpu0.DDQ:count                     20743817435                       # cum count of instructions
system.cpu0.DDQ:rate                                3                       # average number of instructions
system.cpu0.DIS:chain_creation.start_dist
     Inst has no outstanding IDEPS            0      0.00%            # Reason that chain head was created
      IDEP chain reached max depth            0      0.00%            # Reason that chain head was created
                    Inst is a load            0      0.00%            # Reason that chain head was created
  Chain has multiple chained IDEPS            0      0.00%            # Reason that chain head was created
system.cpu0.DIS:chain_creation.end_dist
system.cpu0.DIS:chain_head_frac                     0                       # fraction of insts that are chain heads
system.cpu0.DIS:chain_heads                         0                       # number insts that are chain heads
system.cpu0.DIS:chains_insuf                        0                       # number of times thread had insuf chains
system.cpu0.DIS:chains_insuf_rate                   0                       # rate that thread had insuf chains
system.cpu0.DIS:count                       788090890                       # cumulative count of dispatched insts
system.cpu0.DIS:insufficient_chains                 0                       # Number of instances where dispatch stopped
system.cpu0.DIS:mod_n_stall_avg_free         no value                       # avg free slots per cycle
system.cpu0.DIS:mod_n_stall_frac                    0                       # avg stalls per cycle
system.cpu0.DIS:mod_n_stall_free                    0                       # free slots when dispatch stalled due to mod-n
system.cpu0.DIS:mod_n_stalls                        0                       # cycles where dispatch stalled due to mod-n
system.cpu0.DIS:one_rdy_insts                       0                       # number of 2-op insts w/ one rdy op
system.cpu0.DIS:one_rdy_ratio                no value                       # fraction of 2-op insts w/ one ready op
system.cpu0.DIS:op_count                    807080530                       # number of operations dispatched
system.cpu0.DIS:op_rate                      0.109770                       # dispatched operations per cycle
system.cpu0.DIS:rate                         0.107187                       # dispatched_insts per cycle
system.cpu0.DIS:second_choice_clust                 0                       # Number of instructions dispatched to second-choice cluster
system.cpu0.DIS:second_choice_stall                 0                       # Number of instructions stalled when first choice not available
system.cpu0.DIS:serialize_stall_cycles        5326566                       # count of cycles dispatch stalled for serializing inst
system.cpu0.DIS:serializing_insts              350329                       # count of serializing insts dispatched
system.cpu0.DIS:two_input_insts                     0                       # Number of two input instructions queued
system.cpu0.DIS:two_input_ratio                     0                       # fraction of all insts having 2 inputs
system.cpu0.FETCH:branch_count              264700516                       # Number of branches fetched
system.cpu0.FETCH:branch_rate                0.036002                       # Number of branch fetches per cycle
system.cpu0.FETCH:chance_pct                        1                       # Percentage of all fetch chances
system.cpu0.FETCH:chances                   141165384                       # Number of fetch opportunities
system.cpu0.FETCH:choice                    141165384                       # Number of times we fetched from our first choice
system.cpu0.FETCH:count                     852275587                       # Number of instructions fetched
system.cpu0.FETCH:decisions                 141165384                       # number of times the fetch stage chose between threads
system.cpu0.FETCH:idle_cycles              7211304458                       # number of cycles where fetch stage was idle
system.cpu0.FETCH:idle_icache_blocked_cycles            0                       # number of cycles where fetch was idle due to icache blocked
system.cpu0.FETCH:idle_rate                     98.08                       # percent of cycles fetch stage was idle
system.cpu0.FETCH:prio_changes                      0                       # Number of times priorities were changed
system.cpu0.FETCH:rate                       0.115917                       # Number of inst fetches per cycle
system.cpu0.FETCH:rate_dist.start_dist                         # Number of instructions fetched each cycle (Total)
system.cpu0.FETCH:rate_dist.samples         141165384                      
system.cpu0.FETCH:rate_dist.min_value               0                      
                               0       123053      8.72%           
                               1      1594816    112.98%           
                               2       682663     48.36%           
                               3      2504050    177.38%           
                               4       882695     62.53%           
                               5       468297     33.17%           
                               6    121373350   8597.95%           
                               7       600750     42.56%           
                               8     12935710    916.35%           
system.cpu0.FETCH:rate_dist.max_value               8                      
system.cpu0.FETCH:rate_dist.end_dist

system.cpu0.FETCH:rate_dist_0.start_dist                       # Number of instructions fetched each cycle (Thread 0)
system.cpu0.FETCH:rate_dist_0.samples       141165384                      
system.cpu0.FETCH:rate_dist_0.min_value             0                      
                               0       123053      8.72%           
                               1      1594816    112.98%           
                               2       682663     48.36%           
                               3      2504050    177.38%           
                               4       882695     62.53%           
                               5       468297     33.17%           
                               6    121373350   8597.95%           
                               7       600750     42.56%           
                               8     12935710    916.35%           
system.cpu0.FETCH:rate_dist_0.max_value             8                      
system.cpu0.FETCH:rate_dist_0.end_dist

system.cpu0.IFQ:count                      5281763072                       # cumulative IFQ occupancy
system.cpu0.IFQ:full_count                  158931583                       # cumulative IFQ full count
system.cpu0.IFQ:full_rate                    2.161608                       # fraction of time (cycle's) IFQ was full
system.cpu0.IFQ:latency                      6.701972                       # avg IFQ occupant latency (cycle's)
system.cpu0.IFQ:occupancy                    0.718366                       # avg IFQ occupancy (inst's)
system.cpu0.IFQ:qfull_iq_occ               1722366222                       # Number of insts in IQ when fetch-queue full
system.cpu0.IFQ:qfull_iq_occ_dist_0.start_dist                     # Number of insts in IQ when fetch-queue full
system.cpu0.IFQ:qfull_iq_occ_dist_0.samples     33210878                      
system.cpu0.IFQ:qfull_iq_occ_dist_0.min_value            0                      
                               0      4963851   1494.65%           
                              10       708406    213.31%           
                              20       508383    153.08%           
                              30       635673    191.41%           
                              40       772473    232.60%           
                              50       355138    106.93%           
                              60     25266954   7608.04%           
system.cpu0.IFQ:qfull_iq_occ_dist_0.max_value           64                      
system.cpu0.IFQ:qfull_iq_occ_dist_0.end_dist

system.cpu0.IFQ:qfull_rob_occ              3094796875                       # Number of insts in ROB when fetch-queue full
system.cpu0.IFQ:qfull_rob_occ_dist_0.start_dist                     # Number of insts in ROB when fetch-queue full
system.cpu0.IFQ:qfull_rob_occ_dist_0.samples     33210878                      
system.cpu0.IFQ:qfull_rob_occ_dist_0.min_value            1                      
                               0       417906    125.83%           
                              10       650609    195.90%           
                              20       508806    153.20%           
                              30       182722     55.02%           
                              40       123109     37.07%           
                              50        92217     27.77%           
                              60      3096696    932.43%           
                              70      1335461    402.12%           
                              80       570694    171.84%           
                              90     20713923   6237.09%           
                             100       400791    120.68%           
                             110       536821    161.64%           
                             120      4581123   1379.40%           
                             130            0      0.00%           
system.cpu0.IFQ:qfull_rob_occ_dist_0.max_value          128                      
system.cpu0.IFQ:qfull_rob_occ_dist_0.end_dist

system.cpu0.IQ:cap_events                           0                       # number of cycles where IQ cap was active
system.cpu0.IQ:cap_inst                             0                       # number of instructions held up by IQ cap
system.cpu0.IQ:residence:(null).start_dist                     # cycles from dispatch to issue
system.cpu0.IQ:residence:(null).samples          4226                      
system.cpu0.IQ:residence:(null).min_value            1                      
                               0         4112   9730.24%   9730.24%
                               2          113    267.39%   9997.63%
                               4            0      0.00%   9997.63%
                               6            0      0.00%   9997.63%
                               8            1      2.37%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%