config.ini

linux下基于c++的处理器仿真平台。具有处理器流水线

[root]
type=Root
children=cpu0 cpu1 cpu2 cpu3 dram hier toMembus workload
checkpoint=
clock=200000000
max_tick=0
output_file=cout
progress_interval=0

[cpu0]
type=SimpleCPU
children=dcache icache
clock=1
dcache=cpu0.dcache
defer_registration=false
function_trace=false
function_trace_start=0
icache=cpu0.icache
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
width=1
workload=workload

[cpu0.dcache]
type=BaseCache
children=protocol
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
do_copy=false
hash_delay=1
hier=hier
in_bus=Null
latency=1
lifo=false
max_miss_count=0
mem_trace=Null
mshrs=4
out_bus=toMembus
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=cpu0.dcache.protocol
repl=Null
size=65536
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8

[cpu0.dcache.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=msi

[cpu0.icache]
type=BaseCache
children=protocol
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
do_copy=false
hash_delay=1
hier=hier
in_bus=Null
latency=1
lifo=false
max_miss_count=0
mem_trace=Null
mshrs=4
out_bus=toMembus
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=cpu0.icache.protocol
repl=Null
size=65536
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8

[cpu0.icache.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=msi

[cpu1]
type=SimpleCPU
children=dcache icache
clock=1
dcache=cpu1.dcache
defer_registration=false
function_trace=false
function_trace_start=0
icache=cpu1.icache
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
width=1
workload=workload

[cpu1.dcache]
type=BaseCache
children=protocol
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
do_copy=false
hash_delay=1
hier=hier
in_bus=Null
latency=1
lifo=false
max_miss_count=0
mem_trace=Null
mshrs=4
out_bus=toMembus
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=cpu1.dcache.protocol
repl=Null
size=65536
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8

[cpu1.dcache.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=msi

[cpu1.icache]
type=BaseCache
children=protocol
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
do_copy=false
hash_delay=1
hier=hier
in_bus=Null
latency=1
lifo=false
max_miss_count=0
mem_trace=Null
mshrs=4
out_bus=toMembus
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=cpu1.icache.protocol
repl=Null
size=65536
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8

[cpu1.icache.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=msi

[cpu2]
type=SimpleCPU
children=dcache icache
clock=1
dcache=cpu2.dcache
defer_registration=false
function_trace=false
function_trace_start=0
icache=cpu2.icache
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
width=1
workload=workload

[cpu2.dcache]
type=BaseCache
children=protocol
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
do_copy=false
hash_delay=1
hier=hier
in_bus=Null
latency=1
lifo=false
max_miss_count=0
mem_trace=Null
mshrs=4
out_bus=toMembus
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=cpu2.dcache.protocol
repl=Null
size=65536
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8

[cpu2.dcache.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=msi

[cpu2.icache]
type=BaseCache
children=protocol
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
do_copy=false
hash_delay=1
hier=hier
in_bus=Null
latency=1
lifo=false
max_miss_count=0
mem_trace=Null
mshrs=4
out_bus=toMembus
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=cpu2.icache.protocol
repl=Null
size=65536
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8

[cpu2.icache.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=msi

[cpu3]
type=SimpleCPU
children=dcache icache
clock=1
dcache=cpu3.dcache
defer_registration=false
function_trace=false
function_trace_start=0
icache=cpu3.icache
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
width=1
workload=workload

[cpu3.dcache]
type=BaseCache
children=protocol
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
do_copy=false
hash_delay=1
hier=hier
in_bus=Null
latency=1
lifo=false
max_miss_count=0
mem_trace=Null
mshrs=4
out_bus=toMembus
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=cpu3.dcache.protocol
repl=Null
size=65536
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8

[cpu3.dcache.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=msi

[cpu3.icache]
type=BaseCache
children=protocol
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
do_copy=false
hash_delay=1
hier=hier
in_bus=Null
latency=1
lifo=false
max_miss_count=0
mem_trace=Null
mshrs=4
out_bus=toMembus
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=cpu3.icache.protocol
repl=Null
size=65536
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8

[cpu3.icache.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=msi

[dram]
type=BaseMemory
addr_range=0:18446744073709551615
compressed=false
do_writes=false
hier=hier
in_bus=toMembus
latency=100
snarf_updates=true
uncacheable_latency=1000

[hier]
type=HierParams
do_data=false
do_events=false

[serialize]
count=10
cycle=0
dir=cpt.%012d
period=0

[stats]
descriptions=true
dump_cycle=0
dump_period=0
dump_reset=false
ignore_events=
mysql_db=
mysql_host=
mysql_password=
mysql_user=
project_name=test
simulation_name=test
simulation_sample=0
text_compat=true
text_file=m5stats.txt

[toMembus]
type=Bus
clock=1
hier=hier
width=16

[trace]
bufsize=0
dump_on_exit=false
file=cout
flags=
ignore=
start=0

[workload]
type=LiveProcess
cmd=/n/poolfs/z/home/stever/bk/m5-test/test-progs/radix/bin/radix -n262144 -p4
env=
input=cin
output=cout