m5stats.txt

linux下基于c++的处理器仿真平台。具有处理器流水线

cpu.IFQ:qfull_rob_occ_dist_3.samples           151433                      
cpu.IFQ:qfull_rob_occ_dist_3.min_value              0                      
                               0        60935   4023.89%           
                              10        22510   1486.47%           
                              20        37788   2495.36%           
                              30        14267    942.13%           
                              40         6869    453.60%           
                              50         3747    247.44%           
                              60         2417    159.61%           
                              70          877     57.91%           
                              80          730     48.21%           
                              90          161     10.63%           
                             100          255     16.84%           
                             110           65      4.29%           
                             120          142      9.38%           
                             130           53      3.50%           
                             140           67      4.42%           
                             150           56      3.70%           
                             160           79      5.22%           
                             170           26      1.72%           
                             180          282     18.62%           
                             190          107      7.07%           
                             200            0      0.00%           
cpu.IFQ:qfull_rob_occ_dist_3.max_value            196                      
cpu.IFQ:qfull_rob_occ_dist_3.end_dist

cpu.IQ:cap_events                                   0                       # number of cycles where IQ cap was active
cpu.IQ:cap_events_0                                 0                       # number of cycles where IQ cap was active
cpu.IQ:cap_events_1                                 0                       # number of cycles where IQ cap was active
cpu.IQ:cap_events_2                                 0                       # number of cycles where IQ cap was active
cpu.IQ:cap_events_3                                 0                       # number of cycles where IQ cap was active
cpu.IQ:cap_inst                                     0                       # number of instructions held up by IQ cap
cpu.IQ:cap_inst_0                                   0                       # number of instructions held up by IQ cap
cpu.IQ:cap_inst_1                                   0                       # number of instructions held up by IQ cap
cpu.IQ:cap_inst_2                                   0                       # number of instructions held up by IQ cap
cpu.IQ:cap_inst_3                                   0                       # number of instructions held up by IQ cap
cpu.IQ:residence:(null).start_dist                             # cycles from dispatch to issue
cpu.IQ:residence:(null).samples                     0                      
cpu.IQ:residence:(null).min_value                   0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.IQ:residence:(null).max_value                   0                      
cpu.IQ:residence:(null).end_dist

cpu.IQ:residence:IntAlu.start_dist                             # cycles from dispatch to issue
cpu.IQ:residence:IntAlu.samples                907745                      
cpu.IQ:residence:IntAlu.min_value                   1                      
                               0        94277   1038.58%   1038.58%
                               2       130835   1441.32%   2479.90%
                               4       113889   1254.64%   3734.54%
                               6       138767   1528.70%   5263.24%
                               8       117121   1290.24%   6553.48%
                              10       104372   1149.79%   7703.28%
                              12        75232    828.78%   8532.05%
                              14        51688    569.41%   9101.47%
                              16        32090    353.51%   9454.98%
                              18        18243    200.97%   9655.95%
                              20         7881     86.82%   9742.77%
                              22         3258     35.89%   9778.66%
                              24         1396     15.38%   9794.04%
                              26          606      6.68%   9800.71%
                              28          405      4.46%   9805.18%
                              30          319      3.51%   9808.69%
                              32          232      2.56%   9811.25%
                              34          201      2.21%   9813.46%
                              36          152      1.67%   9815.14%
                              38          102      1.12%   9816.26%
                              40           76      0.84%   9817.10%
                              42           72      0.79%   9817.89%
                              44           81      0.89%   9818.78%
                              46           81      0.89%   9819.67%
                              48           86      0.95%   9820.62%
                              50           78      0.86%   9821.48%
                              52           97      1.07%   9822.55%
                              54          142      1.56%   9824.11%
                              56          102      1.12%   9825.24%
                              58           89      0.98%   9826.22%
                              60          133      1.47%   9827.68%
                              62           92      1.01%   9828.70%
                              64          104      1.15%   9829.84%
                              66          126      1.39%   9831.23%
                              68          134      1.48%   9832.71%
                              70          115      1.27%   9833.97%
                              72           95      1.05%   9835.02%
                              74          101      1.11%   9836.13%
                              76           87      0.96%   9837.09%
                              78           97      1.07%   9838.16%
                              80           94      1.04%   9839.19%
                              82          112      1.23%   9840.43%
                              84          107      1.18%   9841.61%
                              86           90      0.99%   9842.60%
                              88          120      1.32%   9843.92%
                              90          104      1.15%   9845.07%
                              92          128      1.41%   9846.48%
                              94          134      1.48%   9847.95%
                              96          146      1.61%   9849.56%
                              98          137      1.51%   9851.07%
cpu.IQ:residence:IntAlu.overflows               13519                      
cpu.IQ:residence:IntAlu.max_value                1150                      
cpu.IQ:residence:IntAlu.end_dist

cpu.IQ:residence:IntMult.start_dist                            # cycles from dispatch to issue
cpu.IQ:residence:IntMult.samples                  271                      
cpu.IQ:residence:IntMult.min_value                  1                      
                               0            9    332.10%    332.10%
                               2           29   1070.11%   1402.21%
                               4           32   1180.81%   2583.03%
                               6           72   2656.83%   5239.85%
                               8           49   1808.12%   7047.97%
                              10           37   1365.31%   8413.28%
                              12           14    516.61%   8929.89%
                              14            9    332.10%   9261.99%