📄 m5stats.txt
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---------- Begin Simulation Statistics ----------cpu.COM:IPB 6.499129 # Committed instructions per branchcpu.COM:IPB_0 5.674010 # Committed instructions per branchcpu.COM:IPB_1 6.325511 # Committed instructions per branchcpu.COM:IPB_2 7.861951 # Committed instructions per branchcpu.COM:IPB_3 6.211598 # Committed instructions per branchcpu.COM:IPC 3.876943 # Committed instructions per cyclecpu.COM:IPC_0 1.448143 # Committed instructions per cyclecpu.COM:IPC_1 0.298595 # Committed instructions per cyclecpu.COM:IPC_2 1.445097 # Committed instructions per cyclecpu.COM:IPC_3 0.685108 # Committed instructions per cyclecpu.COM:branches 199780 # Number of branches committedcpu.COM:branches_0 85475 # Number of branches committedcpu.COM:branches_1 15809 # Number of branches committedcpu.COM:branches_2 61558 # Number of branches committedcpu.COM:branches_3 36938 # Number of branches committedcpu.COM:bw_lim_avg 18.1304 # Avg number not committed in cycles BW limitedcpu.COM:bw_lim_avg_0 5.0126 # Avg number not committed in cycles BW limitedcpu.COM:bw_lim_avg_1 1.6390 # Avg number not committed in cycles BW limitedcpu.COM:bw_lim_avg_2 8.0078 # Avg number not committed in cycles BW limitedcpu.COM:bw_lim_avg_3 3.4709 # Avg number not committed in cycles BW limitedcpu.COM:bw_lim_events 81482 # number cycles where commit BW limit reachedcpu.COM:bw_lim_rate 4.4112 # Average number not committed due to BW (over all cycles)cpu.COM:bw_lim_rate_0 1.2196 # Average number not committed due to BW (over all cycles)cpu.COM:bw_lim_rate_1 0.3988 # Average number not committed due to BW (over all cycles)cpu.COM:bw_lim_rate_2 1.9483 # Average number not committed due to BW (over all cycles)cpu.COM:bw_lim_rate_3 0.8445 # Average number not committed due to BW (over all cycles)cpu.COM:bw_lim_stdev_0_mean 5.0126 # standard deviation of bw_lim_avg valuecpu.COM:bw_lim_stdev_0_stdev 7.3592 # standard deviation of bw_lim_avg value**Ignore: cpu.COM:bw_lim_stdev_0_TOT 81482.0000 # standard deviation of bw_lim_avg valuecpu.COM:bw_lim_stdev_1_mean 1.6390 # standard deviation of bw_lim_avg valuecpu.COM:bw_lim_stdev_1_stdev 7.0014 # standard deviation of bw_lim_avg value**Ignore: cpu.COM:bw_lim_stdev_1_TOT 81482.0000 # standard deviation of bw_lim_avg valuecpu.COM:bw_lim_stdev_2_mean 8.0078 # standard deviation of bw_lim_avg valuecpu.COM:bw_lim_stdev_2_stdev 16.8989 # standard deviation of bw_lim_avg value**Ignore: cpu.COM:bw_lim_stdev_2_TOT 81482.0000 # standard deviation of bw_lim_avg valuecpu.COM:bw_lim_stdev_3_mean 3.4709 # standard deviation of bw_lim_avg valuecpu.COM:bw_lim_stdev_3_stdev 11.6528 # standard deviation of bw_lim_avg value**Ignore: cpu.COM:bw_lim_stdev_3_TOT 81482.0000 # standard deviation of bw_lim_avg valuecpu.COM:bw_limited 1477303 # number of insts not committed due to BW limitscpu.COM:bw_limited_0 408440 # number of insts not committed due to BW limitscpu.COM:bw_limited_1 133553 # number of insts not committed due to BW limitscpu.COM:bw_limited_2 652492 # number of insts not committed due to BW limitscpu.COM:bw_limited_3 282818 # number of insts not committed due to BW limitscpu.COM:committed_per_cycle.start_dist # Number of insts commited each cyclecpu.COM:committed_per_cycle.samples 267738 cpu.COM:committed_per_cycle.min_value 0 0 1060 39.59% 1 40186 1500.94% 2 32779 1224.29% 3 30294 1131.48% 4 26389 985.63% 5 18226 680.74% 6 15746 588.11% 7 11603 433.37% 8 91455 3415.84% cpu.COM:committed_per_cycle.max_value 8 cpu.COM:committed_per_cycle.end_distcpu.COM:count 1298396 # Number of instructions committedcpu.COM:count_0 484986 # Number of instructions committedcpu.COM:count_1 100000 # Number of instructions committedcpu.COM:count_2 483966 # Number of instructions committedcpu.COM:count_3 229444 # Number of instructions committedcpu.COM:loads 336320 # Number of loads committedcpu.COM:loads_0 147538 # Number of loads committedcpu.COM:loads_1 26002 # Number of loads committedcpu.COM:loads_2 123857 # Number of loads committedcpu.COM:loads_3 38923 # Number of loads committedcpu.COM:membars 0 # Number of memory barriers committedcpu.COM:membars_0 0 # Number of memory barriers committedcpu.COM:membars_1 0 # Number of memory barriers committedcpu.COM:membars_2 0 # Number of memory barriers committedcpu.COM:membars_3 0 # Number of memory barriers committedcpu.COM:refs 482160 # Number of memory references committedcpu.COM:refs_0 195357 # Number of memory references committedcpu.COM:refs_1 36320 # Number of memory references committedcpu.COM:refs_2 179689 # Number of memory references committedcpu.COM:refs_3 70794 # Number of memory references committedcpu.COM:stores 145840 # Number of stores committedcpu.COM:stores_0 47819 # Number of stores committedcpu.COM:stores_1 10318 # Number of stores committedcpu.COM:stores_2 55832 # Number of stores committedcpu.COM:stores_3 31871 # Number of stores committedcpu.COM:swp_count 2253 # Number of s/w prefetches committedcpu.COM:swp_count_0 0 # Number of s/w prefetches committedcpu.COM:swp_count_1 248 # Number of s/w prefetches committedcpu.COM:swp_count_2 16 # Number of s/w prefetches committedcpu.COM:swp_count_3 1989 # Number of s/w prefetches committedcpu.DDQ:count 81821878 # cum count of instructionscpu.DDQ:count_0 25114574 # cum count of instructionscpu.DDQ:count_1 16388649 # cum count of instructionscpu.DDQ:count_2 23831760 # cum count of instructionscpu.DDQ:count_3 16486895 # cum count of instructionscpu.DDQ:rate 244 # average number of instructionscpu.DDQ:rate_0 75 # average number of instructionscpu.DDQ:rate_1 49 # average number of instructionscpu.DDQ:rate_2 71 # average number of instructionscpu.DDQ:rate_3 49 # average number of instructionscpu.DIS:chain_creation.start_dist Inst has no outstanding IDEPS 0 0.00% # Reason that chain head was created IDEP chain reached max depth 0 0.00% # Reason that chain head was created Inst is a load 0 0.00% # Reason that chain head was created Chain has multiple chained IDEPS 0 0.00% # Reason that chain head was createdcpu.DIS:chain_creation.end_distcpu.DIS:chain_head_frac 0 # fraction of insts that are chain headscpu.DIS:chain_head_frac_0 0 # fraction of insts that are chain headscpu.DIS:chain_head_frac_1 0 # fraction of insts that are chain headscpu.DIS:chain_head_frac_2 0 # fraction of insts that are chain headscpu.DIS:chain_head_frac_3 0 # fraction of insts that are chain headscpu.DIS:chain_heads 0 # number insts that are chain headscpu.DIS:chain_heads_0 0 # number insts that are chain headscpu.DIS:chain_heads_1 0 # number insts that are chain headscpu.DIS:chain_heads_2 0 # number insts that are chain headscpu.DIS:chain_heads_3 0 # number insts that are chain headscpu.DIS:chains_insuf 0 # number of times thread had insuf chainscpu.DIS:chains_insuf_0 0 # number of times thread had insuf chainscpu.DIS:chains_insuf_1 0 # number of times thread had insuf chainscpu.DIS:chains_insuf_2 0 # number of times thread had insuf chainscpu.DIS:chains_insuf_3 0 # number of times thread had insuf chainscpu.DIS:chains_insuf_rate 0 # rate that thread had insuf chainscpu.DIS:chains_insuf_rate_0 0 # rate that thread had insuf chainscpu.DIS:chains_insuf_rate_1 0 # rate that thread had insuf chainscpu.DIS:chains_insuf_rate_2 0 # rate that thread had insuf chainscpu.DIS:chains_insuf_rate_3 0 # rate that thread had insuf chainscpu.DIS:count 1577787 # cumulative count of dispatched instscpu.DIS:count_0 581127 # cumulative count of dispatched instscpu.DIS:count_1 153361 # cumulative count of dispatched instscpu.DIS:count_2 524474 # cumulative count of dispatched instscpu.DIS:count_3 318825 # cumulative count of dispatched instscpu.DIS:insufficient_chains 0 # Number of instances where dispatch stoppedcpu.DIS:mod_n_stall_avg_free no value # avg free slots per cyclecpu.DIS:mod_n_stall_avg_free_0 no value # avg free slots per cyclecpu.DIS:mod_n_stall_avg_free_1 no value # avg free slots per cyclecpu.DIS:mod_n_stall_avg_free_2 no value # avg free slots per cyclecpu.DIS:mod_n_stall_avg_free_3 no value # avg free slots per cyclecpu.DIS:mod_n_stall_frac 0 # avg stalls per cyclecpu.DIS:mod_n_stall_frac_0 0 # avg stalls per cyclecpu.DIS:mod_n_stall_frac_1 0 # avg stalls per cyclecpu.DIS:mod_n_stall_frac_2 0 # avg stalls per cyclecpu.DIS:mod_n_stall_frac_3 0 # avg stalls per cyclecpu.DIS:mod_n_stall_free 0 # free slots when dispatch stalled due to mod-ncpu.DIS:mod_n_stall_free_0 0 # free slots when dispatch stalled due to mod-ncpu.DIS:mod_n_stall_free_1 0 # free slots when dispatch stalled due to mod-ncpu.DIS:mod_n_stall_free_2 0 # free slots when dispatch stalled due to mod-ncpu.DIS:mod_n_stall_free_3 0 # free slots when dispatch stalled due to mod-ncpu.DIS:mod_n_stalls 0 # cycles where dispatch stalled due to mod-ncpu.DIS:mod_n_stalls_0 0 # cycles where dispatch stalled due to mod-ncpu.DIS:mod_n_stalls_1 0 # cycles where dispatch stalled due to mod-ncpu.DIS:mod_n_stalls_2 0 # cycles where dispatch stalled due to mod-ncpu.DIS:mod_n_stalls_3 0 # cycles where dispatch stalled due to mod-ncpu.DIS:one_rdy_insts 0 # number of 2-op insts w/ one rdy opcpu.DIS:one_rdy_insts_0 0 # number of 2-op insts w/ one rdy opcpu.DIS:one_rdy_insts_1 0 # number of 2-op insts w/ one rdy opcpu.DIS:one_rdy_insts_2 0 # number of 2-op insts w/ one rdy opcpu.DIS:one_rdy_insts_3 0 # number of 2-op insts w/ one rdy opcpu.DIS:one_rdy_ratio no value # fraction of 2-op insts w/ one ready opcpu.DIS:one_rdy_ratio_0 no value # fraction of 2-op insts w/ one ready opcpu.DIS:one_rdy_ratio_1 no value # fraction of 2-op insts w/ one ready op
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