📄 m5stats.txt
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L2.overall_mshr_miss_latency 3710814474 # number of overall MSHR miss cyclesL2.overall_mshr_miss_rate 0.482194 # mshr miss rate for overall accessesL2.overall_mshr_misses 2508859 # number of overall MSHR missesL2.overall_mshr_uncacheable_latency 1139292124 # number of overall MSHR uncacheable cyclesL2.overall_mshr_uncacheable_misses 772303 # number of overall MSHR uncacheable missesL2.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cacheL2.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshrL2.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queueL2.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer leftL2.prefetcher.num_hwpf_identified 0 # number of hwpf identifiedL2.prefetcher.num_hwpf_issued 0 # number of hwpf issuedL2.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocatedL2.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual pageL2.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation timeL2.read_accesses 3418963 # number of read accesses(hits+misses)L2.read_avg_miss_latency 1494.177291 # average read miss latencyL2.read_avg_mshr_miss_latency 1479.084506 # average read mshr miss latencyL2.read_avg_mshr_uncacheable_latency 1459.572436 # average read mshr uncacheable latencyL2.read_hits 910104 # number of read hitsL2.read_miss_latency 3748680144 # number of read miss cyclesL2.read_miss_rate 0.733807 # miss rate for read accessesL2.read_misses 2508859 # number of read missesL2.read_mshr_miss_latency 3710814474 # number of read MSHR miss cyclesL2.read_mshr_miss_rate 0.733807 # mshr miss rate for read accessesL2.read_mshr_misses 2508859 # number of read MSHR missesL2.read_mshr_uncacheable 502545 # number of read MSHR uncacheableL2.read_mshr_uncacheable_latency 733500830 # number of read MSHR uncacheable cyclesL2.replacements 2507811 # number of replacementsL2.sampled_refs 2508835 # Sample count of references to valid blocks.L2.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutionsL2.tagsinuse 1023.839977 # Cycle average of tags in useL2.total_refs 1656931 # Total number of references to valid blocks.L2.warmup_cycle 88880 # Cycle when the warmup percentage was hit.L2.write_avg_mshr_uncacheable_latency 1504.278998 # average write mshr uncacheable latencyL2.write_mshr_uncacheable 269758 # number of write MSHR uncacheableL2.write_mshr_uncacheable_latency 405791294 # number of write MSHR uncacheable cyclesL2.writeback_accesses 1784046 # number of writeback accesses(hits+misses)L2.writeback_hits 746827 # number of writeback hitsL2.writeback_miss_rate 0.581386 # miss rate for writeback accessesL2.writeback_misses 1037219 # number of writeback missesL2.writeback_mshr_miss_rate 0.581386 # mshr miss rate for writeback accessesL2.writeback_mshr_misses 1037219 # number of writeback MSHR missesL2.writebacks 619178 # number of writebacksSDRAM.accesses 4937558 # total number of accessesSDRAM.bytes_requested 161069521 # total number of bytes requestedSDRAM.bytes_sent 161069521 # total number of bytes sentSDRAM.compressed_responses 0 # total number of accesses that are compressedcheckMem.page_count 0 # total number of pages allocatedcheckMem.page_mem 0 # total size of memory pages allocatedcheckMem.ptab_accesses 7750317 # total page table accessesscheckMem.ptab_miss_rate 0.0000 # first level page table miss ratecheckMem.ptab_misses 0 # total first level page table misseshost_mem_usage 11940 # Number of bytes of host memory usedhost_seconds 94.13 # Real time elapsed on the hosthost_tick_rate 1505804 # Simulator tick rate (ticks/s)mainMem.page_count 0 # total number of pages allocatedmainMem.page_mem 0 # total size of memory pages allocatedmainMem.ptab_accesses 4975700 # total page table accessessmainMem.ptab_miss_rate 0.0000 # first level page table miss ratemainMem.ptab_misses 0 # total first level page table missessim_freq 200000000 # Frequency of simulated tickssim_seconds 0.708703 # Number of seconds simulatedsim_ticks 141740621 # Number of ticks simulatedtest.num_copies 0 # number of copy accesses completedtest.num_reads 5000000 # number of read accesses completedtest.num_writes 2690724 # number of write accesses completedtoL2Bus.addr_idle_cycles 95493726 # number of cycles bus was idletoL2Bus.addr_idle_fraction 0.673722 # fraction of time addr bus was idletoL2Bus.addr_queued 11.896186 # average queueing delay seen by bus requesttoL2Bus.addr_queued_cycles 74292445 # total number of queued cycles for all requeststoL2Bus.addr_requests 6245064 # number of transmissions on bustoL2Bus.bus_blocked 2423331 # number of times bus was blockedtoL2Bus.bus_blocked_cycles 70599516 # number of cycles bus was blockedtoL2Bus.bus_blocked_fraction 0.498090 # fraction of time bus was blockedtoL2Bus.data_idle_cycles 129790052 # number of cycles bus was idletoL2Bus.data_idle_fraction 0.915687 # fraction of time data bus was idletoL2Bus.data_queued 2.026279 # average queueing delay seen by bus requesttoL2Bus.data_queued_cycles 7946006 # total number of queued cycles for all requeststoL2Bus.data_requests 3921477 # number of transmissions on bustoL2Bus.null_grants 0 # number of null grants (wasted cycles)toMemBus.addr_idle_cycles 120911260 # number of cycles bus was idletoMemBus.addr_idle_fraction 0.853046 # fraction of time addr bus was idletoMemBus.addr_queued 13.743065 # average queueing delay seen by bus requesttoMemBus.addr_queued_cycles 71564414 # total number of queued cycles for all requeststoMemBus.addr_requests 5207311 # number of transmissions on bustoMemBus.bus_blocked 86 # number of times bus was blockedtoMemBus.bus_blocked_cycles 176 # number of cycles bus was blockedtoMemBus.bus_blocked_fraction 0.000001 # fraction of time bus was blockedtoMemBus.data_idle_cycles 72007748 # number of cycles bus was idletoMemBus.data_idle_fraction 0.508025 # fraction of time data bus was idletoMemBus.data_queued 6.440302 # average queueing delay seen by bus requesttoMemBus.data_queued_cycles 19394152 # total number of queued cycles for all requeststoMemBus.data_requests 3011373 # number of transmissions on bustoMemBus.null_grants 0 # number of null grants (wasted cycles)toMemBusSlow.addr_idle_cycles 100082144 # number of cycles bus was idletoMemBusSlow.addr_idle_fraction 0.706094 # fraction of time addr bus was idletoMemBusSlow.addr_queued 52.248851 # average queueing delay seen by bus requesttoMemBusSlow.addr_queued_cycles 272075966 # total number of queued cycles for all requeststoMemBusSlow.addr_requests 5207310 # number of transmissions on bustoMemBusSlow.bus_blocked 0 # number of times bus was blockedtoMemBusSlow.bus_blocked_cycles 0 # number of cycles bus was blockedtoMemBusSlow.bus_blocked_fraction 0 # fraction of time bus was blockedtoMemBusSlow.data_idle_cycles 2274928 # number of cycles bus was idletoMemBusSlow.data_idle_fraction 0.016050 # fraction of time data bus was idletoMemBusSlow.data_queued 1159.723131 # average queueing delay seen by bus requesttoMemBusSlow.data_queued_cycles 3492358924 # total number of queued cycles for all requeststoMemBusSlow.data_requests 3011373 # number of transmissions on bustoMemBusSlow.null_grants 0 # number of null grants (wasted cycles)---------- End Simulation Statistics ----------⌨️ 快捷键说明
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