📄 m5stats.txt
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---------- Begin Simulation Statistics ----------DL1.avg_blocked_cycles_no_mshrs 34.934755 # average number of cycles each access was blockedDL1.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blockedDL1.avg_refs 1.023562 # Average number of references to valid blocks.DL1.blocked_no_mshrs 3847712 # number of cycles access was blockedDL1.blocked_no_targets 0 # number of cycles access was blockedDL1.blocked_cycles_no_mshrs 134418876 # number of cycles access was blockedDL1.blocked_cycles_no_targets 0 # number of cycles access was blockedDL1.cache_copies 0 # number of cache copies performedDL1.demand_accesses 6918459 # number of demand (read+write) accessesDL1.demand_avg_miss_latency 1107.482446 # average overall miss latencyDL1.demand_avg_mshr_miss_latency 1104.482468 # average overall mshr miss latencyDL1.demand_hits 3499495 # number of demand (read+write) hitsDL1.demand_miss_latency 3786442615 # number of demand (read+write) miss cyclesDL1.demand_miss_rate 0.494180 # miss rate for demand accessesDL1.demand_misses 3418964 # number of demand (read+write) missesDL1.demand_mshr_hits 0 # number of demand (read+write) MSHR hitsDL1.demand_mshr_miss_latency 3776185798 # number of demand (read+write) MSHR miss cyclesDL1.demand_mshr_miss_rate 0.494180 # mshr miss rate for demand accessesDL1.demand_mshr_misses 3418964 # number of demand (read+write) MSHR missesDL1.fast_writes 0 # number of fast writes performedDL1.mshr_cap_events 0 # number of times MSHR cap was activatedDL1.no_allocate_misses 0 # Number of misses that were no-allocateDL1.overall_accesses 6918459 # number of overall (read+write) accessesDL1.overall_avg_miss_latency 1107.482446 # average overall miss latencyDL1.overall_avg_mshr_miss_latency 1104.482468 # average overall mshr miss latencyDL1.overall_avg_mshr_uncacheable_latency 1501.551120 # average overall mshr uncacheable latencyDL1.overall_hits 3499495 # number of overall hitsDL1.overall_miss_latency 3786442615 # number of overall miss cyclesDL1.overall_miss_rate 0.494180 # miss rate for overall accessesDL1.overall_misses 3418964 # number of overall missesDL1.overall_mshr_hits 0 # number of overall MSHR hitsDL1.overall_mshr_miss_latency 3776185798 # number of overall MSHR miss cyclesDL1.overall_mshr_miss_rate 0.494180 # mshr miss rate for overall accessesDL1.overall_mshr_misses 3418964 # number of overall MSHR missesDL1.overall_mshr_uncacheable_latency 1159652435 # number of overall MSHR uncacheable cyclesDL1.overall_mshr_uncacheable_misses 772303 # number of overall MSHR uncacheable missesDL1.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cacheDL1.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshrDL1.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queueDL1.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer leftDL1.prefetcher.num_hwpf_identified 0 # number of hwpf identifiedDL1.prefetcher.num_hwpf_issued 0 # number of hwpf issuedDL1.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocatedDL1.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual pageDL1.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation timeDL1.read_accesses 4497481 # number of read accesses(hits+misses)DL1.read_avg_miss_latency 1108.111977 # average read miss latencyDL1.read_avg_mshr_miss_latency 1105.112003 # average read mshr miss latencyDL1.read_avg_mshr_uncacheable_latency 1478.685592 # average read mshr uncacheable latencyDL1.read_hits 2275478 # number of read hitsDL1.read_miss_latency 2462228138 # number of read miss cyclesDL1.read_miss_rate 0.494055 # miss rate for read accessesDL1.read_misses 2222003 # number of read missesDL1.read_mshr_miss_latency 2455562186 # number of read MSHR miss cyclesDL1.read_mshr_miss_rate 0.494055 # mshr miss rate for read accessesDL1.read_mshr_misses 2222003 # number of read MSHR missesDL1.read_mshr_uncacheable 502545 # number of read MSHR uncacheableDL1.read_mshr_uncacheable_latency 743106051 # number of read MSHR uncacheable cyclesDL1.replacements 3417915 # number of replacementsDL1.sampled_refs 3418939 # Sample count of references to valid blocks.DL1.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutionsDL1.tagsinuse 1023.824024 # Cycle average of tags in useDL1.total_refs 3499495 # Total number of references to valid blocks.DL1.warmup_cycle 107334 # Cycle when the warmup percentage was hit.DL1.write_accesses 2420978 # number of write accesses(hits+misses)DL1.write_avg_miss_latency 1106.313804 # average write miss latencyDL1.write_avg_mshr_miss_latency 1103.313819 # average write mshr miss latencyDL1.write_avg_mshr_uncacheable_latency 1544.148400 # average write mshr uncacheable latencyDL1.write_hits 1224017 # number of write hitsDL1.write_miss_latency 1324214477 # number of write miss cyclesDL1.write_miss_rate 0.494412 # miss rate for write accessesDL1.write_misses 1196961 # number of write missesDL1.write_mshr_miss_latency 1320623612 # number of write MSHR miss cyclesDL1.write_mshr_miss_rate 0.494412 # mshr miss rate for write accessesDL1.write_mshr_misses 1196961 # number of write MSHR missesDL1.write_mshr_uncacheable 269758 # number of write MSHR uncacheableDL1.write_mshr_uncacheable_latency 416546384 # number of write MSHR uncacheable cyclesDL1.writebacks 1784046 # number of writebacksL2.avg_blocked_cycles_no_mshrs 28.820161 # average number of cycles each access was blockedL2.avg_blocked_cycles_no_targets no value # average number of cycles each access was blockedL2.avg_refs 0.660438 # Average number of references to valid blocks.L2.blocked_no_mshrs 2364398 # number of cycles access was blockedL2.blocked_no_targets 0 # number of cycles access was blockedL2.blocked_cycles_no_mshrs 68142332 # number of cycles access was blockedL2.blocked_cycles_no_targets 0 # number of cycles access was blockedL2.cache_copies 0 # number of cache copies performedL2.demand_accesses 3418963 # number of demand (read+write) accessesL2.demand_avg_miss_latency 1494.177291 # average overall miss latencyL2.demand_avg_mshr_miss_latency 1479.084506 # average overall mshr miss latencyL2.demand_hits 910104 # number of demand (read+write) hitsL2.demand_miss_latency 3748680144 # number of demand (read+write) miss cyclesL2.demand_miss_rate 0.733807 # miss rate for demand accessesL2.demand_misses 2508859 # number of demand (read+write) missesL2.demand_mshr_hits 0 # number of demand (read+write) MSHR hitsL2.demand_mshr_miss_latency 3710814474 # number of demand (read+write) MSHR miss cyclesL2.demand_mshr_miss_rate 0.733807 # mshr miss rate for demand accessesL2.demand_mshr_misses 2508859 # number of demand (read+write) MSHR missesL2.fast_writes 0 # number of fast writes performedL2.mshr_cap_events 0 # number of times MSHR cap was activatedL2.no_allocate_misses 0 # Number of misses that were no-allocateL2.overall_accesses 5203009 # number of overall (read+write) accessesL2.overall_avg_miss_latency 1057.134148 # average overall miss latencyL2.overall_avg_mshr_miss_latency 1479.084506 # average overall mshr miss latencyL2.overall_avg_mshr_uncacheable_latency 1475.188008 # average overall mshr uncacheable latencyL2.overall_hits 1656931 # number of overall hitsL2.overall_miss_latency 3748680144 # number of overall miss cyclesL2.overall_miss_rate 0.681544 # miss rate for overall accessesL2.overall_misses 3546078 # number of overall missesL2.overall_mshr_hits 0 # number of overall MSHR hits⌨️ 快捷键说明
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