smdk2412.c

来自「s3c6410的 Uboot 代码, 感兴趣的可以看看呀」· C语言 代码 · 共 740 行 · 第 1/2 页

/*
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <[e-mail]>
 *
 * (C) Copyright 2002
 * David Mueller, ELSOFT AG, <[e-mail]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <regs.h>
#include <linux/mtd/onenand_regs.h>

#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

/* ------------------------------------------------------------------------- */
static inline void delay(unsigned long loops)
{
	__asm__ volatile ("1:\n" "subs %0, %1, #1\n" "bne 1b":"=r" (loops):"0"(loops));
}

/*
 * Miscellaneous platform dependent initialisations
 */

static void cs8900_pre_init(void)
{
	BANK_CFG_REG &= ~((1<<5)|(1<<4));	//EBI Setting for SROM
						//BANK4,5 conf. = one NAND/SRAM
	SMBIDCYR5_REG = 0;			//Bank5 Idle cycle ctrl.
	SMBWSTWRR5_REG = 14;			//Bank5 Write Wait State ctrl.
	SMBWSTOENR5_REG = 2;			//Bank5 Output Enable Assertion Delay ctrl.     Tcho?
	SMBWSTWENR5_REG = 2;			//Bank5 Write Enable Assertion Delay ctrl.

	SMBWSTRDR5_REG = 14;			//Bank5 Read Wait State cont. = 14 clk	    Tacc?
	SMBCR5_REG |=  ((1<<2)|(1<<0));		//SMWAIT active High, Read Byte Lane Enabl	    WS1?
	SMBCR5_REG &= ~((3<<20)|(3<<12));	//SMADDRVALID = always High when Read/Write
	SMBCR5_REG &= ~(3<<4);			//Clear Memory Width
	SMBCR5_REG |=  (1<<4);			//Memory Width = 16bit
}

#ifdef CONFIG_ONENAND
static void onenand_pre_init(void)
{
	u16 sysconfig1;
	u16* addr = (u16*)(CFG_ONENAND_BASE+ONENAND_REG_SYS_CFG1);

	GPFDAT_REG = (GPFDAT_REG & ~0x8) | 0x8;

	sysconfig1 = *addr;

	SMBCR1_REG = 0x00303012; // non-burst		// Asynchronous
	*addr = (sysconfig1& ~(0xf<<12))|(0<<15)|(4<<12);

	SMBIDCYR1_REG = 0;
	SMBWSTWRR1_REG = 14;
	SMBWSTOENR1_REG = 2;
	SMBWSTWENR1_REG = 2;
	SMBWSTRDR1_REG = 14;  //14clk
	SMBIDCYR1_REG = 0x0;

	SSMCCR_REG |= ((1<<1)|(1<<0));
}
#endif

/*
 * When NAND is not used as Boot Device
 */
static void nand_pre_init(void)
{
	SMBIDCYR3_REG = 0xf;
	SMBWSTRDR3_REG = 0x1f;
	SMBWSTWRR3_REG = 0x1f;
	SMBWSTOENR3_REG = 0;
	SMBWSTWENR3_REG = 1;
	SMBCR3_REG = 0x00303000;
	SMBSR3_REG = 0;
	SMBWSTBDR3_REG = 0x1f;
}

static void max1718_init(unsigned int voltage)
{
	GPBCON_REG = (GPBCON_REG & ~((3<<20)|(0xf<<14))) | ((1<<20)|(0x5<<14));

	GPBDAT_REG &= ~(1<<7);
	switch(voltage) {
		case 120:
			GPFDAT_REG = (GPFDAT_REG & ~0xf0) | 0xB0;
			break;
		case 125:
			GPFDAT_REG = (GPFDAT_REG & ~0xf0) | 0xA0;
			break;
		case 130:
			GPFDAT_REG = (GPFDAT_REG & ~0xf0) | 0x90;
			break;
		case 135:
			GPFDAT_REG = (GPFDAT_REG & ~0xf0) | 0x80;
			break;
		case 140:
		default:
			GPFDAT_REG = (GPFDAT_REG & ~0xf0) | 0x70;
			break;
	}

	GPBDAT_REG &= ~(1<<8);
	GPBDAT_REG |= (1<<10);
	GPBDAT_REG |= (1<<8);
}

int board_init(void)
{
	max1718_init(VDD_ARM);
	nand_pre_init();
	cs8900_pre_init();
#ifdef CONFIG_ONENAND
	onenand_pre_init();
#endif

	SMBCR4_REG = 0x00000015;
	gd->bd->bi_arch_number = MACH_TYPE;
	gd->bd->bi_boot_params = 0x30000100;

#if 0
	icache_enable();
	dcache_enable();
#endif

	return 0;
}

int dram_init(void)
{
	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
#ifdef CONFIG_SDRAM_16BITS
	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE >> 1;
#else
	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
#endif

	return 0;
}

#ifdef CONFIG_LCD_2412
#define mdelay(x)	udelay(1000*x)
/**************************************************
 Code to initialize the LCD for 2413 SMDK Eval board
 through SPI controlled by GPIO's.
*************************************************/
#ifdef CONFIG_SMDK2412_V14
#define LCD_DEN		(1<<6)
#define LCD_DSERI	(1<<6)
#define LCD_DCLK	(1<<7)
#define LCD_RESET     	(1<<5)


#define LCD_DEN_Lo	{ gpdat = __raw_readl(S3C_GPBDAT); \
					   gpdat &= ~LCD_DEN; \
					   __raw_writel(gpdat, S3C_GPBDAT); \
					 }

#define LCD_DEN_Hi	{ gpdat = __raw_readl(S3C_GPBDAT); \
					   gpdat |= LCD_DEN; \
					   __raw_writel(gpdat, S3C_GPBDAT); \
					 }

#define LCD_DCLK_Lo	{ gpdat = __raw_readl(S3C_GPGDAT); \
					   gpdat &= ~LCD_DCLK; \
					   __raw_writel(gpdat, S3C_GPGDAT); \
					 }

#define LCD_DCLK_Hi	{ gpdat = __raw_readl(S3C_GPGDAT); \
					   gpdat |= LCD_DCLK; \
					   __raw_writel(gpdat, S3C_GPGDAT); \
					 }

#define LCD_DSERI_Lo	{ gpdat = __raw_readl(S3C_GPGDAT); \
					   gpdat &= ~LCD_DSERI; \
					   __raw_writel(gpdat, S3C_GPGDAT); \
					 }

#define LCD_DSERI_Hi	{ gpdat = __raw_readl(S3C_GPGDAT); \
					   gpdat |= LCD_DSERI; \
					   __raw_writel(gpdat, S3C_GPGDAT); \
					 }

#define LCD_RESET_Lo	{ gpdat = __raw_readl(S3C_GPGDAT); \
					   gpdat &= ~LCD_RESET; \
					   __raw_writel(gpdat, S3C_GPGDAT); \
					 }
#define LCD_RESET_Hi	{ gpdat = __raw_readl(S3C_GPGDAT); \
					   gpdat |= LCD_RESET; \
					   __raw_writel(gpdat, S3C_GPGDAT); \
					 }
#else
#define LCD_DEN		(1<<2)
#define LCD_DSERI	(1<<12)
#define LCD_DCLK	(1<<13)
#define LCD_RESET	(0)


#define LCD_DEN_Lo	{ gpdat = __raw_readl(S3C_GPGDAT); \
					   gpdat &= ~LCD_DEN; \
					   __raw_writel(gpdat, S3C_GPGDAT); \
					 }

#define LCD_DEN_Hi	{ gpdat = __raw_readl(S3C_GPGDAT); \
					   gpdat |= LCD_DEN; \
					   __raw_writel(gpdat, S3C_GPGDAT); \
					 }

#define LCD_DCLK_Lo	{ gpdat = __raw_readl(S3C_GPEDAT); \
					   gpdat &= ~LCD_DCLK; \
					   __raw_writel(gpdat, S3C_GPEDAT); \
					 }

#define LCD_DCLK_Hi	{ gpdat = __raw_readl(S3C_GPEDAT); \
					   gpdat |= LCD_DCLK; \
					   __raw_writel(gpdat, S3C_GPEDAT); \
					 }

#define LCD_DSERI_Lo  { gpdat = __raw_readl(S3C_GPEDAT); \
					   gpdat &= ~LCD_DSERI; \
					   __raw_writel(gpdat, S3C_GPEDAT); \
					 }

#define LCD_DSERI_Hi	{ gpdat = __raw_readl(S3C_GPEDAT); \
					   gpdat |= LCD_DSERI; \
  					   __raw_writel(gpdat, S3C_GPEDAT); \
					 }

#define LCD_RESET_Lo	(0)
#define LCD_RESET_Hi	(1)
#endif

void Write_LDI (u16 address, u16 data)
{
	int j;
	unsigned long DELAY = 1;
	u32 gpdat;

	LCD_DEN_Hi;		//      EN = High                                       CS high
//      LCD_DCLK_Lo;
	LCD_DCLK_Hi;		//      SCL High
	LCD_DSERI_Lo;		//      Data Low

	udelay(DELAY);

	LCD_DEN_Lo;		//      EN = Low                                CS Low
	udelay(DELAY);

	LCD_DCLK_Lo;		//      SCL Low

	udelay(DELAY);

	for (j = 7; j >= 0; j--) {
		if ((address >> j) & 0x0001) {	// DATA HIGH or LOW
			LCD_DSERI_Hi;
		}
		else {
			LCD_DSERI_Lo;
		}

		udelay(DELAY);

		LCD_DCLK_Hi;	// CLOCK = High
		udelay(DELAY);

		if (j != 0) {
			LCD_DCLK_Lo;
			udelay(DELAY);	// CLOCK = Low
		}
	}

	LCD_DSERI_Lo;		// Data Low
	udelay(DELAY);

	LCD_DEN_Hi;		//      EN = High
	udelay(DELAY);

	LCD_DEN_Lo;		//      EN = Low
	udelay(DELAY);

	LCD_DCLK_Lo;
	udelay(DELAY);		// CLOCK = Low

	for (j = 7; j >= 0; j--) {
		if ((data >> j) & 0x0001){	// DATA HIGH or LOW
			LCD_DSERI_Hi;
		}
		else {
			LCD_DSERI_Lo;
		}

		udelay(DELAY);

		LCD_DCLK_Hi;	// CLOCK = High
		udelay(DELAY);

		if (j != 0) {
			LCD_DCLK_Lo;
			udelay(DELAY);	// CLOCK = Low
		}
	}

	LCD_DEN_Hi;		// EN = High
	udelay(DELAY);
}

void SetGPIOforLDI(void)
{
	unsigned long gpdn;
	unsigned long gpdat;
	unsigned long gpcon;

#ifdef CONFIG_SMDK2412_V14
	gpdn = __raw_readl(S3C_GPBDN);
	gpdn  |= (0x1<<6);
	__raw_writel(gpdn, S3C_GPBDN);

	gpdn = __raw_readl(S3C_GPGDN);
	gpdn  |= (0x7<<5);
	__raw_writel(gpdn, S3C_GPGDN);

	gpdat = __raw_readl(S3C_GPBDAT);
	gpdat  |= (0x1<<6);
	__raw_writel(gpdat, S3C_GPBDAT);

	gpdat = __raw_readl(S3C_GPGDAT);
	gpdat  |= (0x7<<5);
	__raw_writel(gpdat, S3C_GPGDAT);

	gpcon = __raw_readl(S3C_GPBCON);
	gpcon  &= ~(0x3<<12);
	gpcon |= (0x1<<12);
	__raw_writel(gpcon, S3C_GPBCON);

	gpcon = __raw_readl(S3C_GPGCON);
	gpcon  &= ~(0x3f<<10);
	gpcon |= (0x15<<10);
	__raw_writel(gpcon, S3C_GPGCON);
#else
	gpdn = __raw_readl(S3C_GPEDN);
	gpdn  |= (0x3<<12);
	__raw_writel(gpdn, S3C_GPEDN);

	gpdn = __raw_readl(S3C_GPGDN);
	gpdn  |= (0x1<<2);
	__raw_writel(gpdn, S3C_GPGDN);

	gpdat = __raw_readl(S3C_GPEDAT);