parity.vhd

来自「it is a parity generator」· VHDL 代码 · 共 47 行

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-- Company: 
-- Engineer: 
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-- Create Date:    21:31:07 12/18/2008 
-- Design Name: 
-- Module Name:    parity - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
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-- Dependencies: 
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-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
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   -- Design Name : parity_using_assign
   -- File Name   : parity_using_assign.vhd
   -- Function    : Parity using direct assignment
   -- Coder       : Deepak Kumar Tala (Verilog)
   -- Translator  : Alexander H Pham (VHDL)
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   library ieee;
       use ieee.std_logic_1164.all;
  
  entity parity_using_assign is
      port (
          data_in     :in  std_logic_vector (7 downto 0);
          parity_out  :out std_logic
      );
  end entity;
  
  architecture rtl of parity_using_assign is
      
  begin
  
      parity_out <= (data_in(0) xor data_in(1)) xor
                    (data_in(2) xor data_in(3)) xor
                    (data_in(4) xor data_in(5)) xor
                    (data_in(6) xor data_in(7));
  end architecture;