parity_using_assign.syr

it is a parity generator

Release 9.2i - xst J.36
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: parity_using_assign.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "parity_using_assign.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "parity_using_assign"
Output Format                      : NGC
Target Device                      : Automotive 9500XL

---- Source Options
Top Module Name                    : parity_using_assign
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
Mux Extraction                     : YES
Resource Sharing                   : YES

---- Target Options
Add IO Buffers                     : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Library Search Order               : parity_using_assign.lso
Keep Hierarchy                     : YES
RTL Output                         : Yes
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Verilog 2001                       : YES

---- Other Options
Clock Enable                       : YES
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/rahul/parityassign/parity.vhd" in Library work.
Entity <parity_using_assign> compiled.
Entity <parity_using_assign> (Architecture <rtl>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <parity_using_assign> in library <work> (architecture <rtl>).


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <parity_using_assign> in library <work> (Architecture <rtl>).
Entity <parity_using_assign> analyzed. Unit <parity_using_assign> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <parity_using_assign>.
    Related source file is "C:/rahul/parityassign/parity.vhd".
    Found 1-bit xor8 for signal <parity_out>.
Unit <parity_using_assign> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Xors                                                 : 1
 1-bit xor8                                            : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Xors                                                 : 1
 1-bit xor8                                            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <parity_using_assign> ...

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : parity_using_assign.ngr
Top Level Output File Name         : parity_using_assign
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : YES
Target Technology                  : Automotive 9500XL
Macro Preserve                     : YES
XOR Preserve                       : YES
Clock Enable                       : YES
wysiwyg                            : NO

Design Statistics
# IOs                              : 9

Cell Usage :
# BELS                             : 7
#      XOR2                        : 7
# IO Buffers                       : 9
#      IBUF                        : 8
#      OBUF                        : 1
=========================================================================
CPU : 5.13 / 5.84 s | Elapsed : 5.00 / 6.00 s
 
--> 

Total memory usage is 117236 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)