📄 board_memories.lst
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\ 00000094 00108DE5 STR R1,[SP, #+0]
\ ??BOARD_ConfigureSdram48MHz_3:
\ 00000098 00009DE5 LDR R0,[SP, #+0]
\ 0000009C 1010A0E3 MOV R1,#+16
\ 000000A0 9C1D81E3 ORR R1,R1,#0x2700
\ 000000A4 010050E1 CMP R0,R1
\ 000000A8 0300002A BCS ??BOARD_ConfigureSdram48MHz_4
\ 000000AC 00009DE5 LDR R0,[SP, #+0]
\ 000000B0 010090E2 ADDS R0,R0,#+1
\ 000000B4 00008DE5 STR R0,[SP, #+0]
\ 000000B8 F6FFFFEA B ??BOARD_ConfigureSdram48MHz_3
187
188 WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 1st CBR
\ ??BOARD_ConfigureSdram48MHz_4:
\ 000000BC FF00E0E3 MVN R0,#+255
\ 000000C0 540DC0E3 BIC R0,R0,#0x1500
\ 000000C4 0410A0E3 MOV R1,#+4
\ 000000C8 001080E5 STR R1,[R0, #+0]
189 pSdram[1] = 0x00000001; // Perform CBR
\ 000000CC 0100A0E3 MOV R0,#+1
\ 000000D0 040084E5 STR R0,[R4, #+4]
190
191 WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 2 CBR
\ 000000D4 FF00E0E3 MVN R0,#+255
\ 000000D8 540DC0E3 BIC R0,R0,#0x1500
\ 000000DC 0410A0E3 MOV R1,#+4
\ 000000E0 001080E5 STR R1,[R0, #+0]
192 pSdram[2] = 0x00000002; // Perform CBR
\ 000000E4 0200A0E3 MOV R0,#+2
\ 000000E8 080084E5 STR R0,[R4, #+8]
193
194 WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 3 CBR
\ 000000EC FF00E0E3 MVN R0,#+255
\ 000000F0 540DC0E3 BIC R0,R0,#0x1500
\ 000000F4 0410A0E3 MOV R1,#+4
\ 000000F8 001080E5 STR R1,[R0, #+0]
195 pSdram[3] = 0x00000003; // Perform CBR
\ 000000FC 0300A0E3 MOV R0,#+3
\ 00000100 0C0084E5 STR R0,[R4, #+12]
196
197 WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 4 CBR
\ 00000104 FF00E0E3 MVN R0,#+255
\ 00000108 540DC0E3 BIC R0,R0,#0x1500
\ 0000010C 0410A0E3 MOV R1,#+4
\ 00000110 001080E5 STR R1,[R0, #+0]
198 pSdram[4] = 0x00000004; // Perform CBR
\ 00000114 0400A0E3 MOV R0,#+4
\ 00000118 100084E5 STR R0,[R4, #+16]
199
200 WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 5 CBR
\ 0000011C FF00E0E3 MVN R0,#+255
\ 00000120 540DC0E3 BIC R0,R0,#0x1500
\ 00000124 0410A0E3 MOV R1,#+4
\ 00000128 001080E5 STR R1,[R0, #+0]
201 pSdram[5] = 0x00000005; // Perform CBR
\ 0000012C 0500A0E3 MOV R0,#+5
\ 00000130 140084E5 STR R0,[R4, #+20]
202
203 WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 6 CBR
\ 00000134 FF00E0E3 MVN R0,#+255
\ 00000138 540DC0E3 BIC R0,R0,#0x1500
\ 0000013C 0410A0E3 MOV R1,#+4
\ 00000140 001080E5 STR R1,[R0, #+0]
204 pSdram[6] = 0x00000006; // Perform CBR
\ 00000144 0600A0E3 MOV R0,#+6
\ 00000148 180084E5 STR R0,[R4, #+24]
205
206 WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 7 CBR
\ 0000014C FF00E0E3 MVN R0,#+255
\ 00000150 540DC0E3 BIC R0,R0,#0x1500
\ 00000154 0410A0E3 MOV R1,#+4
\ 00000158 001080E5 STR R1,[R0, #+0]
207 pSdram[7] = 0x00000007; // Perform CBR
\ 0000015C 0700A0E3 MOV R0,#+7
\ 00000160 1C0084E5 STR R0,[R4, #+28]
208
209 WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 8 CBR
\ 00000164 FF00E0E3 MVN R0,#+255
\ 00000168 540DC0E3 BIC R0,R0,#0x1500
\ 0000016C 0410A0E3 MOV R1,#+4
\ 00000170 001080E5 STR R1,[R0, #+0]
210 pSdram[8] = 0x00000008; // Perform CBR
\ 00000174 0800A0E3 MOV R0,#+8
\ 00000178 200084E5 STR R0,[R4, #+32]
211
212 WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_LMR_CMD); // Set LMR operation
\ 0000017C FF00E0E3 MVN R0,#+255
\ 00000180 540DC0E3 BIC R0,R0,#0x1500
\ 00000184 0310A0E3 MOV R1,#+3
\ 00000188 001080E5 STR R1,[R0, #+0]
213 pSdram[9] = 0xcafedede; // Perform LMR burst=1, lat=2
\ 0000018C ........ LDR R0,??DataTable1 ;; 0xcafedede
\ 00000190 240084E5 STR R0,[R4, #+36]
214
215 WRITE(AT91C_BASE_SDRAMC, SDRAMC_TR, (48000000 * 7) / 1000000); // Set Refresh Timer
\ 00000194 FB00E0E3 MVN R0,#+251
\ 00000198 540DC0E3 BIC R0,R0,#0x1500
\ 0000019C 541FA0E3 MOV R1,#+336
\ 000001A0 001080E5 STR R1,[R0, #+0]
216
217 WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NORMAL_CMD); // Set Normal mode
\ 000001A4 FF00E0E3 MVN R0,#+255
\ 000001A8 540DC0E3 BIC R0,R0,#0x1500
\ 000001AC 0010A0E3 MOV R1,#+0
\ 000001B0 001080E5 STR R1,[R0, #+0]
218 pSdram[0] = 0x00000000; // Perform Normal mode
\ 000001B4 0000A0E3 MOV R0,#+0
\ 000001B8 000084E5 STR R0,[R4, #+0]
219 }
\ 000001BC 1380BDE8 POP {R0,R1,R4,PC} ;; return
\ ??BOARD_ConfigureSdram48MHz_0:
\ 000001C0 ........ DC32 ??pinsSdram_1
\ 000001C4 59411132 DC32 0x32114159
\ In section .rodata, align 4
\ ??pinsSdram_1:
\ 00000000 0000FFFF00F8 DC32 4294901760, 0FFFFF800H
\ FFFF
\ 00000008 04000000 DC8 4, 0, 0, 0
220
221
222 //------------------------------------------------------------------------------
223 /// Configures the EBI for NandFlash access. Pins must be configured after or
224 /// before calling this function.
225 //------------------------------------------------------------------------------
\ In section .text, align 4, keep-with-next
226 void BOARD_ConfigureNandFlash(unsigned char busWidth)
227 {
228 // Configure EBI
229 AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_CS3A_SM;
\ BOARD_ConfigureNandFlash:
\ 00000000 E310E0E3 MVN R1,#+227
\ 00000004 401DC1E3 BIC R1,R1,#0x1000
\ 00000008 001091E5 LDR R1,[R1, #+0]
\ 0000000C 081091E3 ORRS R1,R1,#0x8
\ 00000010 E320E0E3 MVN R2,#+227
\ 00000014 402DC2E3 BIC R2,R2,#0x1000
\ 00000018 001082E5 STR R1,[R2, #+0]
230
231 // Configure SMC
232 AT91C_BASE_SMC->SMC_SETUP3 = 0x00000000;
\ 0000001C CF10E0E3 MVN R1,#+207
\ 00000020 4C1DC1E3 BIC R1,R1,#0x1300
\ 00000024 0020A0E3 MOV R2,#+0
\ 00000028 002081E5 STR R2,[R1, #+0]
233 AT91C_BASE_SMC->SMC_PULSE3 = 0x00030003;
\ 0000002C CB10E0E3 MVN R1,#+203
\ 00000030 4C1DC1E3 BIC R1,R1,#0x1300
\ 00000034 0320A0E3 MOV R2,#+3
\ 00000038 C02B82E3 ORR R2,R2,#0x30000
\ 0000003C 002081E5 STR R2,[R1, #+0]
234 AT91C_BASE_SMC->SMC_CYCLE3 = 0x00050005;
\ 00000040 C710E0E3 MVN R1,#+199
\ 00000044 4C1DC1E3 BIC R1,R1,#0x1300
\ 00000048 0520A0E3 MOV R2,#+5
\ 0000004C 502A82E3 ORR R2,R2,#0x50000
\ 00000050 002081E5 STR R2,[R1, #+0]
235 AT91C_BASE_SMC->SMC_CTRL3 = 0x00002003;
\ 00000054 C310E0E3 MVN R1,#+195
\ 00000058 4C1DC1E3 BIC R1,R1,#0x1300
\ 0000005C 0320A0E3 MOV R2,#+3
\ 00000060 802D82E3 ORR R2,R2,#0x2000
\ 00000064 002081E5 STR R2,[R1, #+0]
236
237 if (busWidth == 8) {
\ 00000068 FF0010E2 ANDS R0,R0,#0xFF ;; Zero extend
\ 0000006C 080050E3 CMP R0,#+8
\ 00000070 0600001A BNE ??BOARD_ConfigureNandFlash_0
238
239 AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS;
\ 00000074 C310E0E3 MVN R1,#+195
\ 00000078 4C1DC1E3 BIC R1,R1,#0x1300
\ 0000007C C320E0E3 MVN R2,#+195
\ 00000080 4C2DC2E3 BIC R2,R2,#0x1300
\ 00000084 002092E5 LDR R2,[R2, #+0]
\ 00000088 002081E5 STR R2,[R1, #+0]
\ 0000008C 090000EA B ??BOARD_ConfigureNandFlash_1
240 }
241 else if (busWidth == 16) {
\ ??BOARD_ConfigureNandFlash_0:
\ 00000090 FF0010E2 ANDS R0,R0,#0xFF ;; Zero extend
\ 00000094 100050E3 CMP R0,#+16
\ 00000098 0600001A BNE ??BOARD_ConfigureNandFlash_1
242
243 AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS;
\ 0000009C C310E0E3 MVN R1,#+195
\ 000000A0 4C1DC1E3 BIC R1,R1,#0x1300
\ 000000A4 001091E5 LDR R1,[R1, #+0]
\ 000000A8 401D91E3 ORRS R1,R1,#0x1000
\ 000000AC C320E0E3 MVN R2,#+195
\ 000000B0 4C2DC2E3 BIC R2,R2,#0x1300
\ 000000B4 001082E5 STR R1,[R2, #+0]
244 }
245 }
\ ??BOARD_ConfigureNandFlash_1:
\ 000000B8 1EFF2FE1 BX LR ;; return
246
247 //------------------------------------------------------------------------------
248 /// Configures the EBI for NandFlash access at 48MHz. Pins must be configured
249 /// after or before calling this function.
250 //------------------------------------------------------------------------------
\ In section .text, align 4, keep-with-next
251 void BOARD_ConfigureNandFlash48MHz(unsigned char busWidth)
252 {
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