📄 board_memories.lst
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\ 00000088 0000A0E3 MOV R0,#+0
\ 0000008C 000084E5 STR R0,[R4, #+0]
113
114 for (i = 0; i < 10000; i++);
\ 00000090 0010A0E3 MOV R1,#+0
\ 00000094 00108DE5 STR R1,[SP, #+0]
\ ??BOARD_ConfigureSdram_3:
\ 00000098 00009DE5 LDR R0,[SP, #+0]
\ 0000009C 1010A0E3 MOV R1,#+16
\ 000000A0 9C1D81E3 ORR R1,R1,#0x2700
\ 000000A4 010050E1 CMP R0,R1
\ 000000A8 0300002A BCS ??BOARD_ConfigureSdram_4
\ 000000AC 00009DE5 LDR R0,[SP, #+0]
\ 000000B0 010090E2 ADDS R0,R0,#+1
\ 000000B4 00008DE5 STR R0,[SP, #+0]
\ 000000B8 F6FFFFEA B ??BOARD_ConfigureSdram_3
115
116 WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 1st CBR
\ ??BOARD_ConfigureSdram_4:
\ 000000BC FF00E0E3 MVN R0,#+255
\ 000000C0 540DC0E3 BIC R0,R0,#0x1500
\ 000000C4 0410A0E3 MOV R1,#+4
\ 000000C8 001080E5 STR R1,[R0, #+0]
117 pSdram[1] = 0x00000001; // Perform CBR
\ 000000CC 0100A0E3 MOV R0,#+1
\ 000000D0 040084E5 STR R0,[R4, #+4]
118
119 WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 2 CBR
\ 000000D4 FF00E0E3 MVN R0,#+255
\ 000000D8 540DC0E3 BIC R0,R0,#0x1500
\ 000000DC 0410A0E3 MOV R1,#+4
\ 000000E0 001080E5 STR R1,[R0, #+0]
120 pSdram[2] = 0x00000002; // Perform CBR
\ 000000E4 0200A0E3 MOV R0,#+2
\ 000000E8 080084E5 STR R0,[R4, #+8]
121
122 WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 3 CBR
\ 000000EC FF00E0E3 MVN R0,#+255
\ 000000F0 540DC0E3 BIC R0,R0,#0x1500
\ 000000F4 0410A0E3 MOV R1,#+4
\ 000000F8 001080E5 STR R1,[R0, #+0]
123 pSdram[3] = 0x00000003; // Perform CBR
\ 000000FC 0300A0E3 MOV R0,#+3
\ 00000100 0C0084E5 STR R0,[R4, #+12]
124
125 WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 4 CBR
\ 00000104 FF00E0E3 MVN R0,#+255
\ 00000108 540DC0E3 BIC R0,R0,#0x1500
\ 0000010C 0410A0E3 MOV R1,#+4
\ 00000110 001080E5 STR R1,[R0, #+0]
126 pSdram[4] = 0x00000004; // Perform CBR
\ 00000114 0400A0E3 MOV R0,#+4
\ 00000118 100084E5 STR R0,[R4, #+16]
127
128 WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 5 CBR
\ 0000011C FF00E0E3 MVN R0,#+255
\ 00000120 540DC0E3 BIC R0,R0,#0x1500
\ 00000124 0410A0E3 MOV R1,#+4
\ 00000128 001080E5 STR R1,[R0, #+0]
129 pSdram[5] = 0x00000005; // Perform CBR
\ 0000012C 0500A0E3 MOV R0,#+5
\ 00000130 140084E5 STR R0,[R4, #+20]
130
131 WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 6 CBR
\ 00000134 FF00E0E3 MVN R0,#+255
\ 00000138 540DC0E3 BIC R0,R0,#0x1500
\ 0000013C 0410A0E3 MOV R1,#+4
\ 00000140 001080E5 STR R1,[R0, #+0]
132 pSdram[6] = 0x00000006; // Perform CBR
\ 00000144 0600A0E3 MOV R0,#+6
\ 00000148 180084E5 STR R0,[R4, #+24]
133
134 WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 7 CBR
\ 0000014C FF00E0E3 MVN R0,#+255
\ 00000150 540DC0E3 BIC R0,R0,#0x1500
\ 00000154 0410A0E3 MOV R1,#+4
\ 00000158 001080E5 STR R1,[R0, #+0]
135 pSdram[7] = 0x00000007; // Perform CBR
\ 0000015C 0700A0E3 MOV R0,#+7
\ 00000160 1C0084E5 STR R0,[R4, #+28]
136
137 WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 8 CBR
\ 00000164 FF00E0E3 MVN R0,#+255
\ 00000168 540DC0E3 BIC R0,R0,#0x1500
\ 0000016C 0410A0E3 MOV R1,#+4
\ 00000170 001080E5 STR R1,[R0, #+0]
138 pSdram[8] = 0x00000008; // Perform CBR
\ 00000174 0800A0E3 MOV R0,#+8
\ 00000178 200084E5 STR R0,[R4, #+32]
139
140 WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_LMR_CMD); // Set LMR operation
\ 0000017C FF00E0E3 MVN R0,#+255
\ 00000180 540DC0E3 BIC R0,R0,#0x1500
\ 00000184 0310A0E3 MOV R1,#+3
\ 00000188 001080E5 STR R1,[R0, #+0]
141 pSdram[9] = 0xcafedede; // Perform LMR burst=1, lat=2
\ 0000018C ........ LDR R0,??DataTable1 ;; 0xcafedede
\ 00000190 240084E5 STR R0,[R4, #+36]
142
143 WRITE(AT91C_BASE_SDRAMC, SDRAMC_TR, (BOARD_MCK * 7) / 1000000); // Set Refresh Timer
\ 00000194 FB00E0E3 MVN R0,#+251
\ 00000198 540DC0E3 BIC R0,R0,#0x1500
\ 0000019C B710A0E3 MOV R1,#+183
\ 000001A0 801F81E3 ORR R1,R1,#0x200
\ 000001A4 001080E5 STR R1,[R0, #+0]
144
145 WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NORMAL_CMD); // Set Normal mode
\ 000001A8 FF00E0E3 MVN R0,#+255
\ 000001AC 540DC0E3 BIC R0,R0,#0x1500
\ 000001B0 0010A0E3 MOV R1,#+0
\ 000001B4 001080E5 STR R1,[R0, #+0]
146 pSdram[0] = 0x00000000; // Perform Normal mode
\ 000001B8 0000A0E3 MOV R0,#+0
\ 000001BC 000084E5 STR R0,[R4, #+0]
147 }
\ 000001C0 1380BDE8 POP {R0,R1,R4,PC} ;; return
\ ??BOARD_ConfigureSdram_0:
\ 000001C4 ........ DC32 ??pinsSdram
\ 000001C8 59722285 DC32 0x85227259
\ In section .rodata, align 4
\ ??pinsSdram:
\ 00000000 0000FFFF00F8 DC32 4294901760, 0FFFFF800H
\ FFFF
\ 00000008 04000000 DC8 4, 0, 0, 0
148
149 //------------------------------------------------------------------------------
150 /// Initialize and configure the SDRAM for a 48 MHz MCK (ROM code clock settings)
151 //------------------------------------------------------------------------------
\ In section .text, align 4, keep-with-next
152 void BOARD_ConfigureSdram48MHz()
153 {
\ BOARD_ConfigureSdram48MHz:
\ 00000000 10402DE9 PUSH {R4,LR}
\ 00000004 08D04DE2 SUB SP,SP,#+8
154 volatile unsigned int i;
155 static const Pin pinsSdram = PINS_SDRAM;
156 volatile unsigned int *pSdram = (unsigned int *) AT91C_EBI_SDRAM;
\ 00000008 8005A0E3 MOV R0,#+536870912
\ 0000000C 0040B0E1 MOVS R4,R0
157
158 // Enable corresponding PIOs
159 PIO_Configure(&pinsSdram, 1);
\ 00000010 0110A0E3 MOV R1,#+1
\ 00000014 A4019FE5 LDR R0,??BOARD_ConfigureSdram48MHz_0 ;; ??pinsSdram_1
\ 00000018 ........ BL PIO_Configure
160
161 // Enable EBI chip select for the SDRAM
162 WRITE(AT91C_BASE_MATRIX, MATRIX_EBI, AT91C_MATRIX_CS1A_SDRAMC);
\ 0000001C E300E0E3 MVN R0,#+227
\ 00000020 400DC0E3 BIC R0,R0,#0x1000
\ 00000024 0210A0E3 MOV R1,#+2
\ 00000028 001080E5 STR R1,[R0, #+0]
163
164
165 // CFG Control Register
166 WRITE(AT91C_BASE_SDRAMC, SDRAMC_CR, AT91C_SDRAMC_NC_9
167 | AT91C_SDRAMC_NR_13
168 | AT91C_SDRAMC_CAS_2
169 | AT91C_SDRAMC_NB_4_BANKS
170 | AT91C_SDRAMC_DBW_32_BITS
171 | AT91C_SDRAMC_TWR_1
172 | AT91C_SDRAMC_TRC_4
173 | AT91C_SDRAMC_TRP_1
174 | AT91C_SDRAMC_TRCD_1
175 | AT91C_SDRAMC_TRAS_2
176 | AT91C_SDRAMC_TXSR_3);
\ 0000002C F700E0E3 MVN R0,#+247
\ 00000030 540DC0E3 BIC R0,R0,#0x1500
\ 00000034 88119FE5 LDR R1,??BOARD_ConfigureSdram48MHz_0+0x4 ;; 0x32114159
\ 00000038 001080E5 STR R1,[R0, #+0]
177
178 for (i = 0; i < 1000; i++);
\ 0000003C 0010A0E3 MOV R1,#+0
\ 00000040 00108DE5 STR R1,[SP, #+0]
\ ??BOARD_ConfigureSdram48MHz_1:
\ 00000044 00009DE5 LDR R0,[SP, #+0]
\ 00000048 FA0F50E3 CMP R0,#+1000
\ 0000004C 0300002A BCS ??BOARD_ConfigureSdram48MHz_2
\ 00000050 00009DE5 LDR R0,[SP, #+0]
\ 00000054 010090E2 ADDS R0,R0,#+1
\ 00000058 00008DE5 STR R0,[SP, #+0]
\ 0000005C F8FFFFEA B ??BOARD_ConfigureSdram48MHz_1
179
180 WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NOP_CMD); // Perform NOP
\ ??BOARD_ConfigureSdram48MHz_2:
\ 00000060 FF00E0E3 MVN R0,#+255
\ 00000064 540DC0E3 BIC R0,R0,#0x1500
\ 00000068 0110A0E3 MOV R1,#+1
\ 0000006C 001080E5 STR R1,[R0, #+0]
181 pSdram[0] = 0x00000000;
\ 00000070 0000A0E3 MOV R0,#+0
\ 00000074 000084E5 STR R0,[R4, #+0]
182
183 WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_PRCGALL_CMD); // Set PRCHG AL
\ 00000078 FF00E0E3 MVN R0,#+255
\ 0000007C 540DC0E3 BIC R0,R0,#0x1500
\ 00000080 0210A0E3 MOV R1,#+2
\ 00000084 001080E5 STR R1,[R0, #+0]
184 pSdram[0] = 0x00000000; // Perform PRCHG
\ 00000088 0000A0E3 MOV R0,#+0
\ 0000008C 000084E5 STR R0,[R4, #+0]
185
186 for (i = 0; i < 10000; i++);
\ 00000090 0010A0E3 MOV R1,#+0
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